AR/VR SoC Verification Engineer — Equity + Bonus

Socket.dev; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Job summary

Meta Reality Labs is seeking a Design Verification Engineer to own verification plans for digital logic blocks in AR/VR silicon. You will design constrained-random UVM testbenches for processors, interconnects, memory controllers, and multimedia accelerators, and close functional coverage against design intent.

You will define coverage models, debug RTL simulations, and collaborate with RTL design teams to mitigate verification risks early.

Qualifications

• 6+ years of experience in digital design verification.

Responsibilities

• Develop and own verification plans for digital logic blocks and subsystems within custom AR/VR silicon, covering functional coverage, corner cases, and compliance requirements
• Design and implement constrained-random UVM testbenches to verify complex RTL designs including processors, interconnects, memory controllers, and multimedia accelerators
• Define and close functional coverage models and code coverage metrics to ensure thorough verification of design intent
• Collaborate with RTL design engineers to review microarchitecture specifications and identify verification risks early in the design cycle
• Develop and maintain simulation infrastructure, regression frameworks, and automated test suites to support continuous integration of design changes
• Perform formal verification and property checking on critical design blocks to complement simulation-based verification
• Debug failing simulations and regressions by analyzing waveforms, log files, and RTL code to root-cause design or testbench issues
• Partner with post-silicon validation and firmware teams to develop pre-silicon test content that transitions to hardware bring-up
• Contribute to verification methodology improvements, including reusable verification IP and shared infrastructure across the silicon team
• Track and report verification progress, coverage closure status, and risk areas to design and program management stakeholders

Skills

UVM

Constrained-random testbenches

Python scripting

RTL design verification

SystemVerilog

VHDL

Education

Bachelor's degree in Computer Science, Computer Engineering, or equivalent

Tools

SystemVerilog

VHDL

Python

Job description

Meta Reality Labs is seeking a Design Verification Engineer to own verification plans for digital logic blocks in AR/VR silicon. You will design constrained-random UVM testbenches for processors, interconnects, memory controllers, and multimedia accelerators, and close functional coverage against design intent.

You will define coverage models, debug RTL simulations, and collaborate with RTL design teams to mitigate verification risks early.