Analog Design Intern, RFIC Platforms

Murata Manufacturing Co., Ltd.; San Diego (CA); On-site; USD 44,000 - 80,000; Full time

Job summary

pSemi Corporation, a Murata company, is seeking an Analog Design Intern for Spring 2026 in San Diego, CA. You will assist engineers in designing and developing analog circuits for RFIC products, including model development and circuit block documentation.

The role interfaces with Digital, Layout, Process tech and Modeling teams, offering hands-on experience in analog/mixed-signal design, verification, and IP block modeling in a fast-paced environment.

Qualifications

• Knowledge of analog integrated circuit design.
• Software tools: Cadence, Excel.
• Strength in documentation clarity and completeness.
• Able to work effectively within the group and cross-functionally with other teams.
• Strong sense of urgency to meet task requirements on schedule.

Responsibilities

• Analog/Mixed-Signal Block Design: Work independently and with our engineers on simulation and layout of circuit blocks.
• IP Block Characterization: Work with Characterization engineer to analyze data from circuit block level testing and create test reports.
• Product Support: Build Verilog/Verilog-a models for analog circuit blocks to enable efficient simulations at chip level. Interface with Analog and RFIC design teams as needed to fine tune the models.
• Documentation: Document any design work to educate others on IP block usage.

Skills

Analog IC design

Documentation

Cross-functional collaboration

Urgency to meet deadlines

Education

BSEE or similar

MS/PhD EE RF/Mixed-Signal

Tools

Cadence

Excel

Job description

pSemi Corporation, a Murata company, is seeking an Analog Design Intern for Spring 2026 in San Diego, CA. You will assist engineers in designing and developing analog circuits for RFIC products, including model development and circuit block documentation.

The role interfaces with Digital, Layout, Process tech and Modeling teams, offering hands-on experience in analog/mixed-signal design, verification, and IP block modeling in a fast-paced environment.