AI Silicon TPM: Backend/NPI Lead for Data-Center Chips

Majestic Labs ai; Los Altos (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Majestic Labs is seeking an experienced Silicon Technical Program Manager (TPM) to coordinate backend execution and New Product Introduction for data-center-grade AI chips. You will bridge hardware design, backend implementation, and post-silicon qualification.

Lead multi-chip schedules from RTL freeze through physical implementation, tapeout, and high-volume production. Strong communication across backend design, DFT, and product engineering teams is essential.

Qualifications

• BS in Electrical Engineering, Computer Engineering, or related field with 8+ years silicon engineering experience.
• MS with 6+ years relevant experience.
• Experience in backend implementation tasks.
• Proven track record bringing chips from tape-out to mass production.
• Experience with data-center-grade silicon projects.
• Strong cross-functional collaboration and communication.

Responsibilities

• We bridge hardware design, backend implementation, and post-silicon qualification.
• Drive multi-chip execution schedules from RTL freeze through tapeout and mass production.
• Collaborate with backend design, DFT, and product engineering teams to resolve trade-offs.

Skills

Backend execution

NPI experience

Data-center silicon

Cross-functional collaboration

Technical communication

Education

BS in Electrical/Computer Engineering

MS in related field

Tools

RTL

Physical implementation

Tapeout

DFT

Job description

Majestic Labs is seeking an experienced Silicon Technical Program Manager (TPM) to coordinate backend execution and New Product Introduction for data-center-grade AI chips. You will bridge hardware design, backend implementation, and post-silicon qualification.

Lead multi-chip schedules from RTL freeze through physical implementation, tapeout, and high-volume production. Strong communication across backend design, DFT, and product engineering teams is essential.