AI-Powered Pre-Silicon Verification Engineer

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 115,000 - 213,000; Full time

Benefits offered by this job

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision plans

Job summary

Cadence Design Systems, Inc. is seeking a Pre-Silicon Verification Engineer to advance AI-powered verification methods for next-gen chips.

You will work on the ChipStack AI Super Agent team, collaborating with ML and software engineers to architect and verify designs with up to 10x productivity gains. Requirements include 4+ years in pre-silicon verification (Formal/ SV/UVM/OVM), strong Verilog/SystemVerilog/Python skills, and experience with Jasper, Xcelium, IMC.

Qualifications

• BS with 4+ years of experience OR MS with 2+ years OR new PhD.
• Proven expertise of more than 3 years in at least one pre-silicon ASIC verification methodology (Formal, SV/UVM, or OVM).
• Advanced debugging skills for pre-silicon verification using waveform viewers and analysis tools.
• Experience with industry standard EDA tools (Jasper, Xcelium, IMC).
• Strong programming skills in Verilog, SystemVerilog and Python.
• Excellent communication and team-oriented mindset.
• Exposure to LLMs and ML technologies like RAG, RFT, RL, and Agentic frameworks is a plus.

Responsibilities

• Contribute to machine learning applications in pre-silicon verification methods like formal verification and UVM.
• Develop agentic AI solutions using LLMs to accelerate verification processes.
• Use AI-enhanced EDA tools to improve design and verification lifecycles.
• Engage with customers to understand requirements and craft verification strategies.
• Collaborate with ML and software teams to validate outputs for correctness and efficiency.
• Stay updated on AI-powered verification advances and share knowledge internally.

Skills

ASIC verification

Debugging

Verilog / SystemVerilog

Python

Communication

Team collaboration

LLMs exposure

Education

BS + 4+ years exp

MS + 2+ years exp

New PhD

Tools

Jasper

Xcelium

IMC

Job description

Cadence Design Systems, Inc. is seeking a Pre-Silicon Verification Engineer to advance AI-powered verification methods for next-gen chips.

You will work on the ChipStack AI Super Agent team, collaborating with ML and software engineers to architect and verify designs with up to 10x productivity gains. Requirements include 4+ years in pre-silicon verification (Formal/ SV/UVM/OVM), strong Verilog/SystemVerilog/Python skills, and experience with Jasper, Xcelium, IMC.