AI Memory & Storage Architect: Data Placement Strategy

HP; Houston (TX); On-site; USD 190,000 - 274,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Disability insurance

Employee assistance program

Flexible spending account

Life insurance

Generous paid time off

11 paid holidays

Flexible vacation and sick leave

Job summary

HP is seeking a Distinguished Technologist to define a unified memory/storage data hierarchy for AI workloads and to optimize data placement, movement, and persistence. You will drive strategy roadmaps, partner with software and OS teams, and mentor engineers across multiple disciplines.

The role emphasizes leadership in hardware design and development, industry collaboration, and long-range planning with executive stakeholders.

Qualifications

• Four-year or Graduate Degree in Electrical Engineering, or related discipline.
• Typically has 12+ years of work experience in electrical design and tools, software/packages, architecture of electronic hardware, or related field.

Responsibilities

• Architect memory/storage hierarchy (DRAM, SSD, cache layers).
• Define policies for data placement & movement across tiers (hot vs. cold data).
• Optimize paging, prefetching, and streaming for AI inference/training.
• Partner with SW team to co-optimize models across memory & storage for AI performance.
• Collaborate with OS/runtime teams on data orchestration.

Skills

Memory design

Computer Engineering

Computer Science

Debugging

Electrical Engineering

Electronic Engineering

Electronics

FPGA

Hardware Architecture

Hardware Design

MATLAB

Mechanical Engineering

New Product Development

Oscilloscope

Physics

Printed Circuit Board

Schematic Capture

Simulations

Systems Design

Education

Electrical Engineering degree

Job description

HP is seeking a Distinguished Technologist to define a unified memory/storage data hierarchy for AI workloads and to optimize data placement, movement, and persistence. You will drive strategy roadmaps, partner with software and OS teams, and mentor engineers across multiple disciplines.

The role emphasizes leadership in hardware design and development, industry collaboration, and long-range planning with executive stakeholders.