Distinguished Technologist - Memory/Storage Utilization & Data Placement Architect

HP; Houston (TX); On-site; USD 190,000 - 274,000; Full time

Benefits offered by this job

Health insurance

Dental insurance

Vision insurance

Disability insurance

Employee assistance program

Flexible spending account

Life insurance

Generous paid time off

11 paid holidays

Flexible vacation and sick leave

Job summary

HP is seeking a Distinguished Technologist to define a unified memory/storage data hierarchy for AI workloads and to optimize data placement, movement, and persistence. You will drive strategy roadmaps, partner with software and OS teams, and mentor engineers across multiple disciplines.

The role emphasizes leadership in hardware design and development, industry collaboration, and long-range planning with executive stakeholders.

Qualifications

• Four-year or Graduate Degree in Electrical Engineering, or related discipline.
• Typically has 12+ years of work experience in electrical design and tools, software/packages, architecture of electronic hardware, or related field.

Responsibilities

• Architect memory/storage hierarchy (DRAM, SSD, cache layers).
• Define policies for data placement & movement across tiers (hot vs. cold data).
• Optimize paging, prefetching, and streaming for AI inference/training.
• Partner with SW team to co-optimize models across memory & storage for AI performance.
• Collaborate with OS/runtime teams on data orchestration.

Skills

Memory design

Computer Engineering

Computer Science

Debugging

Electrical Engineering

Electronic Engineering

Electronics

FPGA

Hardware Architecture

Hardware Design

MATLAB

Mechanical Engineering

New Product Development

Oscilloscope

Physics

Printed Circuit Board

Schematic Capture

Simulations

Systems Design

Education

Electrical Engineering degree

Job description

Distinguished Technologist - Memory/Storage Utilization & Data Placement Architect

Description - This role is responsible for defining how memory and storage are jointly utilized as a unified data hierarchy for AI workloads, optimizing data placement, movement, and persistence. This role leverages technical and business expertise to outline strategy roadmaps for the function. The role identifies future growth opportunities and addresses gaps with innovative solutions. The role collaborates closely with various stakeholders, empowers teams to achieve remarkable and consequential outcomes, and spearheads industry-leading research and development.

Responsibilities

• Architect memory/storage hierarchy (DRAM, SSD, cache layers)
• Define policies for data placement & movement across tiers (hot vs. cold data)
• Optimize paging, prefetching, and streaming for AI inference/training
• Partner with SW team to ensure models are co-optimized across memory & storage for max AI performance
• Enable efficient use of storage as memory extension (e.g., spillover, KV cache strategies)
• Collaborate with OS/runtime teams on data orchestration
• Evaluate emerging approaches (unified memory, memory pooling, compression)
• Leverages recognized technical and business expertise to define long-term vision and strategy for electrical hardware design and development across multiple feature areas and divisional boundaries.
• Develops technology roadmaps for electrical/hardware engineering team; identifies gaps and solutions for future growth.
• Communicates strategy and technology roadmaps to executive staff, industry partners and customers.
• Provides innovative solutions and integrates advanced technologies, theories, or techniques with a significant impact across disciplines, championing large projects for long-range goals.
• Provides consultation, design input, and feedback for new product development and design reviews across multiple organizations and architectures.
• Works closely with product management, engineering stakeholders from related departments and empowers the teams to deliver outstanding and impactful results.
• Initiates industry-leading research and development, serving as a recognized lead authority internally and externally.
• Provides mentoring and guidance to less-experienced staff members to set an example of electrical hardware design and development, innovation, and excellence.
• Participates in and provides input on process for selection of future technical leaders.

Education & Experience

• Four-year or Graduate Degree in Electrical Engineering, or any other related discipline or commensurate work experience or demonstrated competence.
• Typically has 12+ years of work experience, preferably in electrical design and tools, software packages, architecture of electronic hardware, or a related field.
• Preferred Certifications NA

Knowledge & Skills

• Memory design
• Computer Engineering
• Computer Science
• Debugging
• Electrical Engineering
• Electronic Engineering
• Electronics
• Field-Programmable Gate Array (FPGA)
• Hardware Architecture
• Hardware Design
• MATLAB
• Mechanical Engineering
• New Product Development
• Oscilloscope
• Physics
• Printed Circuit Board
• Schematic Capture
• Simulations
• Systems Design

Cross-Org Skills

• Effective Communication
• Results Orientation
• Learning Agility
• Digital Fluency
• Customer Centricity

Impact & Scope

Impacts multiple functions and influences long-term strategic direction across multiple disciplines or areas of HP.

Complexity

Invens, develops and introduces new methods and techniques that impact multiple disciplines and work groups.

Disclaimer

This job description describes the general nature and level of work performed in this role. It is not intended to be an exhaustive list of all duties, skills, responsibilities, knowledge, etc. These may be subject to change and additional functions may be assigned as needed by management.

Pay & Benefits

The pay range for this role is 190,000.00 - 274,000.00 annually with additional opportunities for pay in the form of bonus and/or equity (applies to United States of America candidates only). Pay varies by work location, job-related knowledge, skills, and experience.

Benefits

• Health insurance
• Dental insurance
• Vision insurance
• Long term/short term disability insurance
• Employee assistance program
• Flexible spending account
• Life insurance
• Generous time off policies, including; 4-12 weeks fully paid parental leave based on tenure
• 11 paid holidays
• Additional flexible paid vacation and sick leave (US benefits overview)

Job Details

Job - Engineering Schedule - Full time Shift - No shift premium (United States of America) Travel - Relocation.

Equal Opportunity Employer (EEO)

HP, Inc. provides equal employment opportunity to all employees and prospective employees, without regard to race, color, religion, sex, national origin, ancestry, citizenship, sexual orientation, age, disability, or status as a protected veteran, marital status, familial status, physical or mental disability, medical condition, pregnancy, genetic predisposition or carrier status, uniformed service status, political affiliation or any other characteristic protected by applicable national, federal, state, and local law(s). Please be assured that you will not be subject to any adverse treatment if you choose to disclose the information requested. This information is provided voluntarily. The information obtained will be kept in strict confidence. For more information, review HP’s EEO Policy or read about your rights as an applicant under the law here: “Know Your Rights: Workplace Discrimination is Illegal