AI Hardware Reliability Engineer

Rozgoo; San Francisco (CA); On-site; USD 230,000 - 290,000; Full time

Job summary

OpenAI is seeking a highly skilled cross-stack engineer to advance reliability across the chip/platform stack within the Hardware organization. This hands-on contributor will work with chip design, platform design, hardware health, and the ecosystem to architect, implement, and deploy reliable AI accelerator systems.

You will evaluate architecture holistically, identify high-ROI reliability improvements, and translate them into strategy and silicon features.

Qualifications

• Hands-on experience with RTL design and DFT required.
• Empirical data analysis to drive reliability decisions.
• Strong background in reliability modelling across chip/platform stack.

Responsibilities

• Oversee DFX architecture, implementation and execution from concept to high-volume deployment.
• DFX includes testability, reliability, availability and serviceability of AI hardware.
• Build system-level reliability models grounded in empirical data.
• Collaborate with chip and platform teams to implement DFX features and IP.
• Partner with hardware health and platform teams to drive data-driven improvements.

Skills

RTL design

DFT

empirical data analysis

Education

Bachelor's in Electrical Engineering or related

Master's in Electrical Engineering or related

PhD in relevant field

Job description

OpenAI is seeking a highly skilled cross-stack engineer to advance reliability across the chip/platform stack within the Hardware organization. This hands-on contributor will work with chip design, platform design, hardware health, and the ecosystem to architect, implement, and deploy reliable AI accelerator systems.

You will evaluate architecture holistically, identify high-ROI reliability improvements, and translate them into strategy and silicon features.