AI Data Center High-Speed Interconnect Architect

BIZLINK INTERCONNECT TECHNOLOGY ( INDIA ) PRIVATE LIMITED; Fremont (CA); On-site; USD 180,000 - 230,000; Full time

Job summary

BIZLINK INTERCONNECT TECHNOLOGY ( INDIA ) PRIVATE LIMITED in Fremont, CA seeks a senior professional to architect and optimize high-speed interconnects for AI/ML and HPC platforms. You will lead design efforts, collaborate across hardware, system, and software teams, and influence industry standards to advance next-gen interconnects.

The role requires 10+ years in interconnect architecture, expertise in NVLINK/PCIe/CXL, and strong leadership.

Qualifications

• Bachelor’s or Master’s degree in Electrical/Computer Engineering or related discipline.
• 10+ years of experience in high-speed interconnect architecture, signal integrity, or system design.
• Expertise in high-speed protocols (NVLINK, UALINK, PCIe, CXL, Ethernet, InfiniBand, OSFP, OSFP-X).
• Knowledge of signal integrity, power integrity, PCB/package/system design, and related simulation tools.
• Proven experience in participating in or influencing industry standards development.
• Exceptional communication and cross-functional leadership.
• Familiarity with hardware/software co-design and AI/HPC workloads advantageous.

Responsibilities

• Architect and optimize high-speed interconnect solutions for AI/ML and HPC platforms with performance, SI, power, cost, and manufacturability balance.
• Lead technology assessment and selection of interconnect technologies (e.g., NVLINK, PCIe, CXL) for scalability.
• Collaborate with SI/PI engineers to ensure robust high-speed data transmission and EMI/EMC adherence.
• Coordinate with hardware, system, packaging, and software teams to integrate interconnects into AI server architectures.
• Represent the company in standards bodies (OCP, PCI-SIG, IEEE, CXL) and monitor industry trends.
• Engage with hyperscalers, OEMs, and partners to capture requirements and drive solution development.
• Author technical specifications, architecture documents, and contribute to product roadmaps.

Skills

Interconnect architecture

Signal integrity

Power integrity

Standards participation

Cross-functional leadership

Client liaison

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering

Tools

Simulation tools

Job description

• Architectural Design and Optimization: Architect and optimize high-speed interconnect solutions, including backplanes, co-packaged copper, OSFP, OSFP-X, and onboard connectors, for AI/ML and HPC platforms. Achieve equilibrium among performance, signal integrity, power consumption, cost efficiency, and manufacturing feasibility.
• Technology Assessment: Lead the assessment and selection of interconnect technologies (e.g., NVLINK, UALINK, PCIe, CXL), considering evolving standards and future scalability imperatives.
• Signal and Power Integrity Management: Collaborate with signal and power integrity engineers to ensure robust high-speed data transmission and adherence to electrical and EMI/EMC standards.
• Interdepartmental Collaboration: Engage with hardware, system, packaging, and software development teams to integrate interconnect solutions into AI server and rack architectures.
• Industry Standards Participation: Represent the organization in standards bodies (e.g., OCP, PCI-SIG, UALINK, IEEE, CXL Consortium), influence the formulation of next-generation interconnect standards, and monitor industry trends.
• Client and Partner Liaison: Interact with hyperscalers, OEMs, and technology partners to ascertain requirements, address challenges, and facilitate the collaborative development of innovative solutions.
• Technical Documentation and Strategic Planning: Author technical specifications, architecture documents, and contribute to the product roadmap for high-speed interconnects.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Minimum of 10 years of professional experience in high-speed interconnect architecture, signal integrity, or system design for compute, networking, or AI platforms.
• Extensive expertise in high-speed protocols (NVLINK, UALINK, PCIe, CXL, Ethernet, InfiniBand, OSFP, OSFP-X) and advanced connector/cabling technologies.
• Comprehensive knowledge of signal integrity, power integrity, PCB/package/system design, and relevant simulation tools.
• Proven experience in participating in or influencing industry standards development.
• Exceptional communication and cross-functional leadership proficiencies.
• Familiarity with hardware/software co-design and performance analysis for AI/HPC workloads is advantageous.