Advanced Lithography Process Innovator (20nm+)

118-WW TMG MFG OPS; Lehi (UT); On-site; USD 120,000 - 180,000; Full time

Job summary

Texas Instruments’ LFAB in Lehi, Utah invites applications for a Process Development Engineer with deep expertise in advanced-node semiconductor manufacturing. You will help develop and characterize next-generation lithography and patterning processes for 20nm-class logic, including SADP/LELE pitch-doubling and OPC/RET strategies.

You will work across lithography, etch, metrology, and data analytics to optimize CDU, overlay, and defectivity, and to transfer technology from R&D to high-volume

Qualifications

• Master's in Electrical Engineering, Materials Science, Physics, or related field.
• 5+ years in advanced semiconductor process development.
• Hands-on experience with 22nm node or comparable advanced nodes (e.g., 28nm, 14nm).
• Expertise in photolithography and litho-etch integration.
• Knowledge of OPC/RET and dry etch for pattern transfer.
• CD control, overlay challenges, and defect mitigation.

Responsibilities

• Model lithography window and optimize patterning with simulation tools.
• Improve metrology and CDU/overlay performance.
• Collaborate with vendors on materials and tool upgrades.
• Lead technology transfer from R&D to high-volume manufacturing.
• Characterize patterning defects and drive process improvements.
• Interface with design, integration, yield, and manufacturing teams.

Skills

Photolithography

Litho-etch integration

OPC & RET

Dry etch processes

CD control & CDU

Overlay alignment

DOE & SPC

Data analysis (Python)

Lithography modeling

Cross-functional collaboration

Education

Master's in Electrical Engineering, Materials Science, Physics

PhD preferred

Tools

ProLith

S-Litho

JMP

Python

Job description

Texas Instruments’ LFAB in Lehi, Utah invites applications for a Process Development Engineer with deep expertise in advanced-node semiconductor manufacturing. You will help develop and characterize next-generation lithography and patterning processes for 20nm-class logic, including SADP/LELE pitch-doubling and OPC/RET strategies.

You will work across lithography, etch, metrology, and data analytics to optimize CDU, overlay, and defectivity, and to transfer technology from R&D to high-volume