Photolithography Process Development Engineer (Advanced Patterning)

118-WW TMG MFG OPS; Lehi (UT); On-site; USD 120,000 - 180,000; Full time

Job summary

Texas Instruments’ LFAB in Lehi, Utah invites applications for a Process Development Engineer with deep expertise in advanced-node semiconductor manufacturing. You will help develop and characterize next-generation lithography and patterning processes for 20nm-class logic, including SADP/LELE pitch-doubling and OPC/RET strategies.

You will work across lithography, etch, metrology, and data analytics to optimize CDU, overlay, and defectivity, and to transfer technology from R&D to high-volume

Qualifications

• Master's in Electrical Engineering, Materials Science, Physics, or related field.
• 5+ years in advanced semiconductor process development.
• Hands-on experience with 22nm node or comparable advanced nodes (e.g., 28nm, 14nm).
• Expertise in photolithography and litho-etch integration.
• Knowledge of OPC/RET and dry etch for pattern transfer.
• CD control, overlay challenges, and defect mitigation.

Responsibilities

• Model lithography window and optimize patterning with simulation tools.
• Improve metrology and CDU/overlay performance.
• Collaborate with vendors on materials and tool upgrades.
• Lead technology transfer from R&D to high-volume manufacturing.
• Characterize patterning defects and drive process improvements.
• Interface with design, integration, yield, and manufacturing teams.

Skills

Photolithography

Litho-etch integration

OPC & RET

Dry etch processes

CD control & CDU

Overlay alignment

DOE & SPC

Data analysis (Python)

Lithography modeling

Cross-functional collaboration

Education

Master's in Electrical Engineering, Materials Science, Physics

PhD preferred

Tools

ProLith

S-Litho

JMP

Python

Job description

Change the world. Love your job.

We’re at the forefront of an exciting era of semiconductor innovation at Texas Instruments’ LFAB in Lehi, Utah — home to our state-of-the-art 300mm manufacturing facility now ramping our most advanced 28nm analog and embedded process technology in the heart of the Silicon Slopes. As part of our Advanced Technology Development (ATD) organization, you will be challenged with developing and characterizing the next generation node. We are seeking a highly skilled and hands-onProcess Development Engineerwith deep expertise in advanced-node semiconductor manufacturing. This role focuses on the next generation20nm-class logic technologies, with primary responsibility forphotolithography and litho-etch integration, including advanced patterning techniques such aspitch doubling (SADP/LELE). This role will also work directly with the Resolution Enhancement Techniques (RET) team to create Optical Proximity Corrections (OPC) and validate final pattern meets design tolerance.

You will play a critical role in developing, optimizing, and scaling patterning processes to meet aggressive performance, yield, and manufacturability targets. This is a high-impact position working at the intersection of lithography, materials science, and plasma etch.

Responsibilities include:

• Modeling & Simulation:Utilize lithography simulation software (e.g., Prolith, S-Litho) to analyze process windows and optimize patterning results.
• Metrology & Yield Improvement:Utilize advanced metrology (CD-SEM, Overlay, Scatterometry) to identify defects and improve Critical Dimension Uniformity (CDU) and overlay performance.
• Vendor & Subsystem Interaction:Work with equipment vendors to evaluate new materials, photoresists, and tool hardware upgrades.
• Data Analysis & SPC:Analyze process data, identify root cause, and implement robust process improvements. Apply Statistical Process Control (SPC) and Design of Experiments (DOE) to develop new processes to enable Litho shrink processes.
• Pathfinding & Technology Transfer:Define pathfinding activities for new patterning technology, evaluating High NA Immersion for next-generation nodes. Lead technology transfer from R&D to HVM for photolithography processes.
• Photo Process Characterization:Lead development to create next generation Litho Shrink processes for 20nm class logic nodes.
  • Drivelitho-etch integration (LE, LELE, SADP / pitch doubling)for advanced patterning schemes.
  • Develop and implementresolution enhancement techniques (RET) andoptical proximity correction (OPC)strategies.
  • Evaluate and selectmaterials systems, including photoresists, hard masks, and anti-reflective coatings.
  • Characterize and reduce patterning defects, includingline edge roughness (LER), CD variation, and overlay errors.
  • Collaborate closely with Etch team to optimizepattern transfer, profile control, and CD uniformityInterface with cross-functional teams including design, integration, yield, and manufacturing.

Minimum requirements:

• Master's inElectrical Engineering, Materials Science, Physics, or related discipline
• 5+ years of industry experience inadvanced semiconductor process development
• Direct, hands-on experience with22nm nodeor comparable advanced nodes (e.g., 28nm, 14nm)
• Strong expertise in:
  • Photolithography process development and optimization
  • Litho-etch integration (LELE, SADP, pitch splitting/doubling)
  • OPC and Resolution Enhancement Techniques (RET) methodologies
  • Dry etch processesfor pattern transfer
• Deep understanding of:
  • Critical dimension (CD) control and uniformity
  • Overlay and alignment challenges
  • Defectivity mechanisms and mitigation strategies

Preferred qualifications:

• PhD inElectrical Engineering, Materials Science, Physics, or related discipline
• Experience withself-aligned multiple patterning (SAMP, SADP, SAQP)
• Familiarity with advanced nodes below 22nm (e.g., 16/14nm FinFET technologies)
• Experience working in high-volume manufacturing environments (foundry or IDM)
• Exposure to industry-standard modeling and OPC tools
• Strong problem-solving skills with a data-driven approach
• Demonstrated ability to work cross-functionally in fast-paced environments
• Experience with advanced reticle layout and Resolution Enhancement Techniques (RET)
• Demonstrated strong analytical and problem-solving skills, with a collaborative team-player mindset
• Technical Skills:Deep understanding of Immersion lithography, DUV, and multi-patterning processes.Demonstrated ability to Design for Manufacturing
• Software Skills:Proficiency with lithography simulation software (ProLith, S-Litho) and data analysis tools (e.g., JMP, Python)