ADCE Packaging Design Architect

Intel Corporation; Phoenix, Northern (AZ, KY); Hybrid; USD 221,000 - 312,000; Full time

Job summary

Intel Corporation seeks an experienced Packaging Design Architect to drive end-to-end substrate design from concept through tape-out, and to implement physical layout and routing of the package design.

You'll collaborate with silicon and hardware teams to optimize silicon-package-board performance, define substrate design rules, and resolve DRCs while documenting progress in the product lifecycle system.

Qualifications

• Ph.D./master in EE, chemical, mechanical engineering or material science.
• 10+ years with deep knowledge in package, PCB design or IC digital design.
• Strong design, analysis and problem-solving skills.

Responsibilities

• Drive end-to-end substrate design from concept through tape-out.
• Implement physical layout and routing of the package design.
• Perform substrate fit and routing studies to optimize design and cost.
• Collaborate with silicon and hardware teams to optimize performance and pinout.
• Define design rules and resolve DRCs; document in lifecycle system.

Education

Ph.D./master’s in electrical engineering/ chemical engineering/ mechanical engineering or Material Science

Tools

Mentor Cadence tools

Cadence Allegro platform

Mentor Xpedition platform

SPICE/Ansys tools

Job description

## ADCE Packaging Design ArchitectApply: US, Arizona, Phoenix: US, Oregon, Hillsboro: US, Washington, Multiple Cities: US, New Mexico, Albuquerque: US, Massachusetts, Beaver Brook: Full time: Posted Today: End Date: December 31, 2026 (30+ days left to apply): JR0284396# **Job Details:**## Job Description:Drives end-to-end development for substrate design from concept through tape out and implements physical layout and routing of the package design. Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs. Works closely with silicon and hardware teams to optimize silicon-package-board performance and pinout. Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design. Completes documentation and collateral into the product lifecycle management system of record.Required Skills and Experience:* Self-motivated engineer who has strong technical background in design and electrical analysis.* Solid background in semiconductor fabrication and packaging* Strong analytical ability and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions. - Ability to work independently and at various levels of abstraction* Strong organization, time management, and communication skills, self-motivated.* Experience with design and electromagnetic simulation tools: Mentor, Cadence tools, SPICE, Ansys tools etc.* Experience in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity), and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).* Experience and knowledge with assembly process, test and characterization techniques preferred## **Qualifications:*** Ph.D./master’s in electrical engineering/ chemical engineering/ mechanical engineering or Material Science.* 10+ years and in-depth knowledge/background in Package, PCB design, or IC digital design.## Job Type:Experienced Hire## Shift:Shift 1 (United States of America)## Primary Location:US, Arizona, Phoenix## Additional Locations:US, California, Folsom, US, California, Santa Clara, US, Colorado, Fort Collins, US, Massachusetts, Beaver Brook, US, New Mexico, Albuquerque, US, Oregon, Hillsboro, US, Texas, Austin, US, Washington, Multiple Cities## Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.## BenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.**Work Model for this Role**This role will require an on-site presence. \\* Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 06/09/2026