Yield Enhancement Engineer Lead: Defect Reduction 24/7 Ops

Vanguard International Semiconductor Corporation (VIS)

Singapore

On-site

SGD 45,000 - 65,000

Full time

14 days+

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Job summary

Vanguard International Semiconductor Corporation (VIS) is seeking a detail‑oriented YE Associate Engineer to supervise wafer ops and drive yield improvements in a high‑volume fab. You will train engineers, develop SOPs, operate inspection tools (FIB/SEM/EDX, Brightfield/Darkfield), analyze defects, and lead continuous improvement with cross‑module teams.

This on‑site role requires a degree in Electrical/Electronics/Chemical/Materials and 2–8 years' experience; strong EHSS adherence and

Qualifications

Degree in Electrical, Electronics, Chemical or Materials Engineering.
2–8 years of relevant fab experience in high-volume electronics manufacturing.
Strong commitment to EHSS policies and safe workplace practices.
Excellent communication and leadership skills.

Responsibilities

Supervise YE Associate Engineers and wafer tech operators to ensure 24/7 inline shift operation.
Train and certify YE Associate Engineers on recipe creation and defect source knowledge.
Maintain and enhance SOPs/OCAP and participate in internal/external audits.
Operate FIB/SEM/EDX for inline failure analysis.
Create recipes in Brightfield and Darkfield defect inspection tools.
Track inline defect performance by layer/process tool weekly.
Lead defect reduction activities with modules/vendors/equipment teams.
Stop production or shipments to correct quality problems when needed.