Senior Process Engineer — Yield & CMP Optimization Lead

Vanguard International Semiconductor Corporation (VIS)

Singapore

On-site

SGD 60,000 - 90,000

Full time

14 days+

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Job summary

Vanguard International Semiconductor Corporation (VIS) seeks a capable engineer to analyze SPC charts, DOE data, and yield across thin-film CMP processes. You will use JMP, Klarity ACE, PROMIS, and RMS to ensure recipe compliance and drive uptime and quality improvements.

Collaboration with equipment and manufacturing teams is essential to lead cross-functional tasks and resolve complex process issues. Applicants should hold a degree in Electrical/Electronics or related field, with at least 2

Qualifications

Analytical thinking and strong problem-solving abilities are required.
Excellent communication and collaboration with cross-functional teams.
Ability to work under pressure and adapt to fast-paced environments.

Responsibilities

Analyze SPC charts and apply SPACE rules; annotate for quality troubleshooting.
Analyze data (DOE, ET, yield) using JMP, Klarity ACE; improve process yields.
Create SPC charts and modify SLDB using PROMIS; ensure recipe content compliance with RMS.
Lead small cross-functional teams to address yield improvements and excursions.
Drive uptime and OEE improvements in collaboration with Equipment and Manufacturing Engineers.
Facilitate CIP programs to optimize process window, cost, yield, and productivity.
Self-audit and update documentation to meet TS16949 quality requirements.