Senior Engineer ( Yield Enhancement )

Vanguard International Semiconductor Corporation (VIS); Singapore; On-site; SGD 45,000 - 65,000; Full time

Job summary

Vanguard International Semiconductor Corporation (VIS) is seeking a detail‑oriented YE Associate Engineer to supervise wafer ops and drive yield improvements in a high‑volume fab. You will train engineers, develop SOPs, operate inspection tools (FIB/SEM/EDX, Brightfield/Darkfield), analyze defects, and lead continuous improvement with cross‑module teams.

This on‑site role requires a degree in Electrical/Electronics/Chemical/Materials and 2–8 years' experience; strong EHSS adherence and

Qualifications

• Degree in Electrical, Electronics, Chemical or Materials Engineering.
• 2–8 years of relevant fab experience in high-volume electronics manufacturing.
• Strong commitment to EHSS policies and safe workplace practices.
• Excellent communication and leadership skills.

Responsibilities

• Supervise YE Associate Engineers and wafer tech operators to ensure 24/7 inline shift operation.
• Train and certify YE Associate Engineers on recipe creation and defect source knowledge.
• Maintain and enhance SOPs/OCAP and participate in internal/external audits.
• Operate FIB/SEM/EDX for inline failure analysis.
• Create recipes in Brightfield and Darkfield defect inspection tools.
• Track inline defect performance by layer/process tool weekly.
• Lead defect reduction activities with modules/vendors/equipment teams.
• Stop production or shipments to correct quality problems when needed.

Skills

Interpersonal communication

Leadership

Training and mentoring

Cross-functional liaison

Education

Masters or Bachelor Degree in Electrical / Electronics / Chemical / Material Science Engineering

Tools

FIB/SEM/EDX

Brightfield/Darkfield inspection tools

Defect fingerprinting tools

Job description

• To liaise with module engineers on yield performance analysis
• To drive for defect reduction and yield improvement activities

Job Description

• Supervise YE Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation
• Train and certify YE Associate Engineers on recipe creation and defect source knowledge
• Maintain and enhance internal SOP/OCAP and involve in internal;/external audit
• Operate FIB/SEM/EDX for inline failure analysis
• Operate and create recipes in Brightfield, Darkfield and other defect inspection tools
• Perform partition analysis on defect source and detailed reports on issues
• Build and develop defect source land tool’s defect source fingerprinting
• Track inline defect performance by layer/process tool/chamber on weekly basis
• Perform defect characterization by process tools
• Continuous improvement activities on defect reductions with Modules / vendors / equipment team
• Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities
• Provide scan support in low yield investigation & co-work with PI/PE on technology & device specific yield enhancement activities
• Automate daily activities to improve troubleshooting speed of team
• Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems

Job Requirement

• Masters or Bachelor Degree in Electrical / Electronics / Chemical / Material Science Engineering
• 2-8 years of relevant fab work experience in high volume manufacturing of electronics components in an MNC or semi-conductor industry preferred
• Responsible and accountable for complying with and implementing environmental, health, safety and security (EHSS) system, policies, procedures and guidelines that are applicable to your scope of work , thereby maintaining a healthy and safe workplace.
• Excellent interpersonal and communication skills with good leadership capability