Lead Integration Yield Defect Engineer

Vanguard International Semiconductor Corporation (VIS); Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

Vanguard International Semiconductor Corporation (VIS) in Singapore seeks a supervisor for YDD Associate Engineers and wafer tech operators to ensure continuous 24/7 inline operations. You will train engineers on recipes and defect sources, and maintain SOPs while supporting internal and external audits.

You will operate FIB/SEM/EDX for inline failure analysis, create recipes in YDD tools, manage defect data, and drive continuous yield improvements with cross-functional teams.

Qualifications

• Masters or Bachelor Degree in Electrical / Electronics / Chemical / Microelectronics Engineering.
• 5-8 years of relevant work experience in high volume manufacturing of electronics components in an MNC or semi-conductor industry preferred.
• Familiar and experience in defect analysis and yield enhancement in wafer process.
• Excellent interpersonal and communication skills with good leadership capability.
• Strong analytical skills and able to work under pressure in a fast pace environment.
• Proficient with MS Power Point, Excel, Excel VBA, PowerBI.

Responsibilities

• Supervise YDD Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation.
• Train and certify DO Associate Engineers on recipe creation and defect source knowledge.
• Maintain and enhance internal SOP/CAS and involve in internal/external audit.
• Operate FIB/SEM/EDX for inline failure analysis.
• Operate and create recipes in Brightfield, Darkfield and other YDD tools.
• Maintain and housekeep Brightfield, Darkfield and recipes of other YDD tools.
• Perform partition analysis on defect source and detailed reports on issues.
• Build and develop defect source library and tool’s defect source fingerprinting.
• Track inline defect performance by layer/process tool/chamber on weekly basis.
• Perform defect characterization by process tools.
• Continuous improvement activities on defect reductions with Modules / vendors / equipment team.
• Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities.
• Provide scan support in low yield investigation & co-work with PI/YE/PE on technology & device specific yield enhancement activities.
• Automate daily activities to improve troubleshooting speed of team.
• Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems

Skills

Leadership

Analytical skills

Communication

Work under pressure

Team collaboration

Education

Electrical / Electronics / Chemical / Microelectronics Engineering degree

Tools

MS PowerPoint

Excel

Excel VBA

PowerBI

Job description

Vanguard International Semiconductor Corporation (VIS) in Singapore seeks a supervisor for YDD Associate Engineers and wafer tech operators to ensure continuous 24/7 inline operations. You will train engineers on recipes and defect sources, and maintain SOPs while supporting internal and external audits.

You will operate FIB/SEM/EDX for inline failure analysis, create recipes in YDD tools, manage defect data, and drive continuous yield improvements with cross-functional teams.