System-Level Test Architect for Next-Gen Microprocessors

Thundersoft; Singapore; On-site; SGD 180,000 - 240,000; Full time

Job summary

Thundersoft in Singapore is seeking a senior SLT Test Engineer to own test program development for client next‑gen microprocessors. You will work on internal SLT platforms, debug test infrastructure, and create hardware, software, and diagnostics from product definition through manufacturing.

You will drive test coverage, optimize test time, and collaborate with cross‑functional teams to bring up test flows for pre and post‑silicon phases, ensuring quality and rapid issue resolution.

Qualifications

• Mastery of SLT and System Level Test concepts.
• 10+ years of NPI SLT leadership experience.
• Proficient in Windows, Unix, and Linux operating systems.
• Experience with IC test and ASIC bring up and support activities.

Responsibilities

• Drive test solution development and optimize to meet milestones (schedule, test time, yield, cost, quality).
• Lead SLT pattern development, calibration test flows, debugging, and characterization in an NPI Product Engineering team.
• Collaborate with cross‑functional teams to determine SLT coverage, content, and root cause analysis of SLT failures.
• Engage in pre and post silicon phases, plan test flows, bring up coverage, and coordinate hardware checkout.
• Mentor junior engineers and interface with OSAT partners for test program implementation.

Skills

NPI leadership

SLT test patterns

C/C++/Java/Python

Test/debug hardware software

OS kernel/BIOS

Mentoring engineers

Education

Electrical/Electronics, Computer Engineering

Tools

Git

Job description

Thundersoft in Singapore is seeking a senior SLT Test Engineer to own test program development for client next‑gen microprocessors. You will work on internal SLT platforms, debug test infrastructure, and create hardware, software, and diagnostics from product definition through manufacturing.

You will drive test coverage, optimize test time, and collaborate with cross‑functional teams to bring up test flows for pre and post‑silicon phases, ensuring quality and rapid issue resolution.