Staff Digital Design & DFT Engineer

ORIENTAL MATERIALS PTE. LTD.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

ORIENTAL MATERIALS PTE. LTD. is recruiting for a Singapore-based semiconductor development team focused on integrated circuit design and engineering.

The role involves developing device digital control and test logic, linking circuit design with production test, and collaborating with cross-functional teams. Detailed scope will be discussed in interviews under confidentiality agreements. The ideal candidate will bring 4+ years of relevant experience, strong SystemVerilog and DFT skills, and

Qualifications

• Bachelor’s degree in Electrical Engineering, Microelectronics or related discipline.
• Minimum 4 years of relevant experience, with level determined by ownership and demonstrated results.
• Proficient in SystemVerilog, CDC, synthesis and timing analysis, with production or silicon debug experience.
• Experience in RTL design and memory test or DFT integration, with understanding of fault coverage and observability.
• Familiarity with Python/Tcl automation and ability to define digital/analog interfaces with circuit designers.

Responsibilities

• Develop device-side command decode, mode registers, refresh and low-power control. Define timing contracts with the array and I/O teams.
• Implement test modes, failure observability and redundancy repair with product test. Deliver RTL, design checks and a handoff for ATE execution.
• Define state machines and cross-domain handshakes, closing lint, CDC/RDC and applicable synthesis and STA checks.
• Define BIST, redundancy analysis and fuse programming interfaces with architecture, verifying repair loading and test-state transitions.
• Reproduce test issues with DV and ATE engineers and maintain traceable RTL and test-mode releases.

Job description

About the role

We are recruiting for a Singapore-based semiconductor development team focused on integrated circuit design and engineering. Develop device digital control and test logic connecting circuit design with production test. Further technical scope will be discussed during the interview process, subject to appropriate confidentiality arrangements.

Responsibilities

• Develop device-side command decode, mode registers, refresh and low-power control. Define timing contracts with the array and I/O teams.
• Implement test modes, failure observability and redundancy repair with product test. Deliver RTL, design checks and a handoff for ATE execution.
• Define state machines and cross-domain handshakes, closing lint, CDC/RDC and applicable synthesis and STA checks.
• Define BIST, redundancy analysis and fuse programming interfaces with architecture, verifying repair loading and test-state transitions.
• Reproduce test issues with DV and ATE engineers and maintain traceable RTL and test-mode releases.

Required qualifications

• Bachelor’s degree or above in Electrical Engineering, Microelectronics or a related discipline.
• At least 4 years of relevant experience, with level determined by technical ownership and demonstrated results.
• Proficient in SystemVerilog, CDC, synthesis and timing analysis, with production or silicon debug experience.
• Experience in RTL design and memory test or DFT integration, with understanding of fault coverage and observability.
• Familiarity with Python/Tcl automation and ability to define digital/analog interfaces with circuit designers.

Preferred qualifications

• Experience with memory command state machines, memory BIST or fuse-based repair.
• Experience taking designs or engineering solutions through silicon validation and production introduction.

Working arrangements

Singapore-based full-time position. You will collaborate with cross-functional engineering teams and communicate technical work in English. Any travel requirements will be discussed during interviews. Compensation and role level will reflect experience and responsibilities.