Physical Design Engineer

Trulyyy; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Trulyyy in Singapore is seeking a Physical Design Engineer to implement digital circuits and design flows. You will lead end-to-end backend execution from netlist to GDSII and drive full-chip timing analysis, ensuring robust performance across advanced nodes.

Ideal candidates have 2–8 years in physical design, with hands-on tape-outs for large-scale SoCs and exposure to floorplanning or 3D-IC architectures.

Qualifications

• Bachelor’s degree in electronic engineering or semiconductors.
• 2–8 years of experience in physical design at OEMs, ODMs or fabless companies.
• Proven background executing tape-outs for large-scale, low-voltage or intricate SoCs; exposure to top-level floorplanning or 3D-IC architectures is a plus.

Responsibilities

• Lead the end-to-end digital backend execution (netlist to GDSII) and drive full-chip static timing analysis.
• Run SPICE-level simulations on high-priority timing paths.
• Establish, refine and sustain automated design pipelines covering P&R, physical verification, and power integrity for next-gen EDA tools and process nodes.

Skills

Tape-outs experience

Top-level floorplanning

3D-IC architectures

Static timing analysis

Education

Bachelor’s degree in electronic engineering or semiconductors

Tools

SPICE-level simulations

Place-and-route tools

EDA tools familiarity

Job description

Physical Design Engineer

About the Role

Join a global leader in chip design and high end IC components. We are looking for Physical Design Engineers of different seniority levels to implement digital circuits and design flows.

Key Responsibilities

• Lead the end-to-end digital backend execution (from netlist to GDSII), driving full-chip static timing analysis.
• Runn SPICE-level simulations on high-priority timing paths.
• Establish, refine and sustain automated design pipelines covering place-and-route, physical verification, and power integrity to integrate next-generation EDA tools and advanced process nodes.

Requirements

• Bachelor’s degree in electronic engineering or semiconductors
• 2-8 years in Physical design at either OEMs, ODMs, or Fabless companies
• Proven background executing tape-outs for large-scale, low-voltage, or intricate SoCs, with preferred exposure to top-level floorplanning (bump/ESD), advanced technology sign-off baselines, or 3D-IC architectures.

Regrettably, only shortlisted candidates will be notified.

Please note that data provided is for recruitment purposes only.

Business Registration No.: 202004228R | License No.: 20S0118 | EA Registration No.: R2210710