Senior Yield Engineer: Defect Reduction & Optimization

Vanguard International Semiconductor Corporation (VIS); Singapore; On-site; SGD 60,000 - 100,000; Full time

Job summary

Vanguard International Semiconductor Corporation (VIS) is seeking a Senior YE Engineer to supervise inline shift operations and drive for defect reduction and yield improvement. The role includes training technicians, maintaining SOPs, and performing advanced failure analyses with FIB/SEM/EDX to ensure wafer quality.

The ideal candidate holds an engineering degree and has 2–8 years of fab experience in a multinational environment, with strong EHSS compliance and leadership abilities.

Qualifications

• Masters or Bachelor Degree in Electrical / Electronics / Chemical / Material Science Engineering.
• 2-8 years of relevant fab work experience in high volume manufacturing of electronics components in an MNC or front end wafer fab industry preferred.
• Comply with EHSS system, policies, procedures and guidelines to maintain a healthy and safe workplace.
• Excellent interpersonal and communication skills with good leadership capability.
• Team player.

Responsibilities

• Supervise YE Associate Engineers and wafer tech operators for 24/7 inline shift operation.
• Train and certify YE Associate Engineers on recipe creation and defect source knowledge.
• Maintain and enhance internal SOP/OCAP and participate in audits.
• Operate FIB/SEM/EDX for inline failure analysis.
• Operate and create recipes in Brightfield, Darkfield and other defect inspection tools.
• Perform partition analysis on defect source and detailed reports on issues.
• Build and develop defect source land tool's defect source fingerprinting.
• Track inline defect performance by layer/process tool/chamber on weekly basis.
• Perform killer ratio analysis.
• Perform defect characterization by process tools.
• Continuous improvement activities on defect reductions with Modules / vendors / equipment team.
• Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities.
• Provide scan support in low yield investigation & co-work with PI/PE on technology & device specific yield enhancement activities.
• Automate daily activities to improve troubleshooting speed of team.
• Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems.

Skills

Interpersonal skills

Leadership

Team player

Education

Electrical / Electronics / Chemical / Material Science Engineering degree

Job description

Vanguard International Semiconductor Corporation (VIS) is seeking a Senior YE Engineer to supervise inline shift operations and drive for defect reduction and yield improvement. The role includes training technicians, maintaining SOPs, and performing advanced failure analyses with FIB/SEM/EDX to ensure wafer quality.

The ideal candidate holds an engineering degree and has 2–8 years of fab experience in a multinational environment, with strong EHSS compliance and leadership abilities.