Senior Yield Engineering Lead for Integration Defects

Vanguard International Semiconductor Corporation (VIS); Singapore; On-site; SGD 70,000 - 90,000; Full time

Job summary

Vanguard International Semiconductor Corporation (VIS) in Singapore is looking for experienced individuals to supervise Associate Engineers and wafer tech operators, ensuring smooth 24/7 inline operations.

The successful candidate will have a strong background in electrical or microelectronics engineering, coupled with significant experience in defect analysis and yield enhancement. The position requires effective leadership and communication skills, with a focus on continuous improvement.

Qualifications

• 5-8 years of relevant work experience in high volume manufacturing of electronics components in MNC or semi-conductor industry.
• Familiar with defect analysis and yield enhancement in wafer process.
• Strong analytical skills and able to work under pressure in a fast pace environment.

Responsibilities

• Supervise YDD Associate Engineers and wafer tech operators.
• Train and certify DO Associate Engineers on recipe creation.
• Perform defect characterization by process tools.
• Automate daily activities to improve troubleshooting speed.

Skills

Defect analysis

Yield enhancement

Leadership skills

Analytical skills

Communication skills

Education

Masters or Bachelor Degree in Electrical / Electronics / Chemical / Microelectronics Engineering

Tools

MS Power Point

Excel

Excel VBA

Job description

Vanguard International Semiconductor Corporation (VIS) in Singapore is looking for experienced individuals to supervise Associate Engineers and wafer tech operators, ensuring smooth 24/7 inline operations.

The successful candidate will have a strong background in electrical or microelectronics engineering, coupled with significant experience in defect analysis and yield enhancement. The position requires effective leadership and communication skills, with a focus on continuous improvement.