Principal Engineer (Integration Yield Defect)

Vanguard International Semiconductor Corporation (VIS); Singapore; On-site; SGD 78,000 - 112,000; Full time

Job summary

Vanguard International Semiconductor Corporation (VIS) is seeking a senior process engineer to supervise YDD associates and wafer technicians for around-the-clock inline operations. You will train engineers on recipes and defect sources, maintain SOPs, and perform inline failure analysis using FIB/SEM/EDX.

Applicants should have 5–8 years in high-volume electronics manufacturing, strong defect analysis skills, and proficiency with PowerPoint/Excel/VBA and PowerBI.

Qualifications

• Masters or Bachelor Degree in Electrical / Electronics / Chemical / Microelectronics Engineering.
• 5-8 years of relevant work experience in high volume manufacturing of electronics components or semiconductor industry preferred.
• Familiarity with defect analysis and yield enhancement in wafer process.
• Excellent interpersonal and communication skills with leadership capability.
• Strong analytical skills and ability to work under pressure in a fast-paced environment.
• Proficiency with MS PowerPoint, Excel, Excel VBA, PowerBI.

Responsibilities

• Oversee YDD Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation.
• Train and certify DO Associate Engineers on recipe creation and defect source knowledge.
• Maintain and enhance internal SOP/CAS and participate in internal/external audits.
• Operate FIB/SEM/EDX for inline failure analysis.
• Create recipes in Brightfield, Darkfield and other YDD tools; maintain related files.
• Track inline defect performance by layer/process tool/chamber weekly.
• Drive defect reduction with modules, vendors, and equipment teams.
• Liaise with process engineers across modules to troubleshoot inline defects.
• Provide scan support in low yield investigations and collaborate on yield enhancement.

Skills

Defect analysis

Yield enhancement

Leadership

MS PowerPoint

Excel VBA

PowerBI

Automation

SOP/CAS

Education

Electrical/Electronics/Microelectronics Eng

Tools

Brightfield

Darkfield

FIB/SEM/EDX

Job description

• Supervise YDD Associate Engineers and wafer tech operators to ensure smooth 24/7 inline shift operation
• Train and certify DO Associate Engineers on recipe creation and defect source knowledge
• Maintain and enhance internal SOP/CAS and involve in internal;/external audit
• Operate FIB/SEM/EDX for inline failure analysis
• Operate and create recipes in Brightfield, Darkfield and other YDD tools
• Maintain and housekeep Brightfield, Darkfield and recipes of other YDD tools
• Perform partition analysis on defect source and detailed reports on issues
• Build and develop defect source library and tool’s defect source fingerprinting
• Track inline defect performance by layer/process tool/chamber on weekly basis
• Perform defect characterization by process tools
• Continuous improvement activities on defect reductions with Modules / vendors / equipment team
• Liaise with process engineers in different modules to troubleshoot for inline defects and defect reduction activities
• Provide scan support in low yield investigation & co-work with PI/YE/PE on technology & device specific yield enhancement activities
• Automate daily activities to improve troubleshooting speed of team
• Responsible for wafer quality to conform to product requirements and have the authority to stop shipment and stop production to correct quality problems

Job Requirements:

• Masters or Bachelor Degree in Electrical / Electronics / Chemical / Microelectronics Engineering.
• 5-8 years of relevant work experience in high volume manufacturing of electronics components in an MNC or semi-conductor industry preferred.
• Familiar and experience in defect analysis and yield enhancement in wafer process.
• Excellent interpersonal and communication skills with good leadership capability.
• Strong analytical skills and able to work under pressure in a fast pace environment.
• Proficient with MS Power Point, Excel, Excel VBA, PowerBI.