Senior ASIC Implementation Engineer (Synthesis & STA)

Black Sesame Technologies (Singapore) Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Black Sesame Technologies (Singapore) Pte Ltd is seeking a Senior ASIC Implementation Engineer (Synthesis & STA) to contribute to high-performance AI cores and ADAS chips in our Core IP Design Team. You will lead synthesis, low-power implementation, and timing closure in close collaboration with physical design and SoC teams.

Ideal candidates have 3+ years in digital VLSI, proficient in Verilog/SystemVerilog, Synopsys Design Compiler and PrimeTime, UPF flows, and strong scripting skills.

Qualifications

• Degree in Electrical/Computer Engineering or related field.
• 3+ years of relevant industry experience.
• Strong digital design and VLSI knowledge.
• Proficient in Verilog and SystemVerilog.
• Hands-on with Design Compiler and PrimeTime.
• Experience with UPF low-power flows and formal verification.
• Scripting in Tcl, Perl, and Python; able to analyze RTL.
• Strong analytical and communication skills.

Responsibilities

• Lead synthesis and optimization for IP cores focusing on performance, power, and area.
• Collaborate with physical design on floorplanning, placement, routing, timing closure.
• Coordinate with SoC teams on clock, reset, timing, and power requirements.
• Develop and maintain RTL flows for synthesis, formal verification, and STA.
• Support delivery of multiple complex IP blocks and IP-to-SoC integration.
• Analyze results and suggest RTL improvements for higher frequency and lower power.
• Identify opportunities to improve design methodologies and automation.

Skills

Verilog/SystemVerilog

Digital design

Synthesis & STA

Static timing analysis

RTL optimization

Scripting (Tcl/Perl/Python)

Problem-solving

Communication skills

Education

Bachelor’s/Master’s/Ph.D. in Electrical Engineering or Computer Engineering

Tools

Synopsys Design Compiler

Synopsys PrimeTime

Cadence Conformal LEC

Synopsys Formality

Job description

As a Senior ASIC Implementation Engineer (Synthesis & STA) within our Core IP Design Team, you will contribute to the development and production of next-generation, high-performance, power-efficient AI cores and ADAS chips.

This is a highly visible role responsible for synthesis, low-power implementation, timing closure, and close collaboration with physical design and SoC teams. You will play an important role in optimizing our designs for performance, power, and area while helping bring complex products to market efficiently.

Responsibilities:

• Lead synthesis and optimization efforts for IP cores, with a focus on performance, power, and area (PPA).
• Collaborate with the physical design team on floorplanning, placement, routing, and timing closure.
• Work closely with the SoC team on clock, reset, timing, and power-related design requirements.
• Develop, maintain, and enhance synthesis, formal verification, and static timing analysis flows.
• Support the implementation and delivery of multiple complex IP blocks.
• Partner with SoC implementation engineers to integrate IP-level solutions into SoC-level design flows.
• Analyze implementation results and provide recommendations to improve RTL for higher frequency, lower power, and better physical design convergence.
• Identify opportunities to improve design methodologies, automation, and overall engineering efficiency.

Qualification/ Requirements:

• Education: Bachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 3 years of relevant industry experience.
• Solid understanding of digital design and VLSI concepts.
• Proficiency in Verilog and SystemVerilog.
• Hands-on experience with synthesis tools, particularly Synopsys Design Compiler.
• Hands-on experience with static timing analysis using Synopsys PrimeTime.
• Experience with UPF-based low-power design and implementation flows.
• Experience with formal equivalence verification tools such as Cadence Conformal LEC and/or Synopsys Formality.
• Proficiency in scripting languages such as Tcl, Perl, and Python.
• Strong analytical, problem-solving, and communication skills.
• Excellent attention to detail and a strong willingness to learn.

Preferred Skills:

• Experience with physical synthesis and physically aware optimization.
• Strong understanding of physical design concepts, including floorplanning, placement, clock-tree synthesis, routing, and timing closure.
• Ability to review RTL and recommend improvements for timing, power, area, and physical implementation.
• Experience developing AI accelerators, neural-network processors, or other high-performance compute chips.