Senior Silicon Design & Verification Engineer

Advanced Micro Devices, Inc.; Singapore; Hybrid; SGD 90,000 - 120,000; Full time

Benefits offered by this job

Hybrid work

AMD benefits at a glance

Job summary

AMD is seeking an adaptive, self-motivated design verification engineer to join our growing team. You will be a key contributor, delivering high-quality verification for next-generation processors and SOCs while collaborating across global teams.

You will own scan test patterns, partner with test teams, and help advance DFT methods, ATPG tooling, and clock-domain analysis to ensure robust design closure in high-frequency IP environments.

Qualifications

• Experience with design-for-test methodologies, particularly scan test and ATPG with Tessent.
• Strong working knowledge of ATPG tools and their application to pattern generation and fault coverage.
• Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
• Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory built-in self-test concepts.
• Experience with multi-clock and multi-power-domain designs.
• Familiarity with static timing analysis, clock-domain crossing analysis, static power analysis, and physical design closure.
• Experience adapting standard DFT tools or methods to meet performance requirements.

Responsibilities

• Own the generation, validation, and delivery of scan test patterns for next-gen SERDES IPs and SOCs.
• Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
• Improve scan architecture, scan coverage, test models, execution methods, and product quality.
• Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
• Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.
• Address DFT requirements for high-frequency Phy IP designs while minimizing performance impact.
• Resolve complex interactions between intellectual property and system-on-chip design environments across global teams.
• Develop and implement improvements that simplify design complexity and strengthen engineering quality.

Skills

DFT methods

ATPG pattern design

Scan test knowledge

Boundary scan concepts

Multi-clock/power-domain

Static timing & P&R awareness

Cross-team collaboration

Education

Bachelor's or Master's in Computer Engineering or Electrical Engineering

Tools

Tessent flows

ATPG tool suites

Gate-level netlist debugging

Boundary scan tooling

Job description

AMD is seeking an adaptive, self-motivated design verification engineer to join our growing team. You will be a key contributor, delivering high-quality verification for next-generation processors and SOCs while collaborating across global teams.

You will own scan test patterns, partner with test teams, and help advance DFT methods, ATPG tooling, and clock-domain analysis to ensure robust design closure in high-frequency IP environments.