Senior Silicon Design Engineer: PnR, STA & AI-Driven Flow

AMD; Singapore; On-site; SGD 90,000 - 150,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD Singapore’s silicon design team seeks engineers for RTL/netlist-to-GDS work, focusing on floorplanning, power planning, placement and routing. You’ll push timing closure with STA, SDC debugging and ECOs, and support block- and top-level integration with modern EDA tools.

You will use AI-assisted techniques to analyze data, automate workflows and build reusable flows while collaborating with RTL, circuit, integration and CAD teams. Strong problem-solving and data-driven judgment are essential.

Qualifications

• Hands-on experience in PnR, STA and timing closure.
• Experience with SDC development and physical design integration.
• Experience with physical verification and signoff, low-power checks and EM/IR.

Responsibilities

• Own or contribute to RTL/netlist-to-GDS implementation: floorplanning, power planning, placement, CTS, routing, optimization, ECOs and closure.
• Drive timing closure through STA, constraints (SDC) debugging, interface timing analysis and ECO development.
• Support hierarchical physical design and integration at block, subsystem and top level.
• Resolve challenges in timing, congestion, clocking, power, area, signal integrity and physical verification.
• Support signoff: STA, DRC/LVS, antenna, low-power checks and EM/IR.
• Build reusable automation in Tcl, Python, Perl or shell.
• Use AI coding assistants and agentic tools to speed up run analysis, debug, scripting and workflow automation, and share what works across the team. Review and validate all AI output before relying on it.

Skills

PnR

STA

timing closure

physical design

low-power design

EM/IR

debugging

design reuse

Tools

Fusion Compiler

Innovus

PrimeTime

Tempus

StarRC

Calibre

Job description

AMD Singapore’s silicon design team seeks engineers for RTL/netlist-to-GDS work, focusing on floorplanning, power planning, placement and routing. You’ll push timing closure with STA, SDC debugging and ECOs, and support block- and top-level integration with modern EDA tools.

You will use AI-assisted techniques to analyze data, automate workflows and build reusable flows while collaborating with RTL, circuit, integration and CAD teams. Strong problem-solving and data-driven judgment are essential.