AI-Driven Silicon Design & Physical Layout Engineer

Advanced Micro Devices, Inc.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD Singapore hosts a design team delivering RTL/netlist-to-GDS flows, spanning floorplanning, power planning, placement, and timing convergence. You will work with AI-assisted workflows and modern EDA tools to accelerate delivery and ensure high-quality signoff.

The role focuses on owning blocks, subsystems, or integration efforts with a strong automation and AI-centric mindset, applying data-driven analysis and engineering judgment to validate results across RTL, CAD, and physical design teams.

Qualifications

• Hands-on experience in one or more of: PnR, STA and timing closure, SDC development, physical design integration, physical verification and signoff, low-power design, EM/IR.
• Synopsys and/or Cadence tools, such as Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC or Calibre.
• Experience debugging complex design or flow problems.
• Advanced nodes and hierarchical designs are an advantage.
• Experience building reusable flows or methodologies is highly desirable.

Responsibilities

• Own or contribute to RTL/netlist-to-GDS implementation: floorplanning, power planning, placement, CTS, routing, optimization, ECOs and closure.
• Drive timing closure through STA, constraints (SDC) debugging, interface timing analysis and ECO development.
• Support hierarchical physical design and integration at block, subsystem and top level.
• Resolve challenges in timing, congestion, clocking, power, area, signal integrity and physical verification.
• Support signoff: STA, DRC/LVS, antenna, low-power checks and EM/IR.
• Build reusable automation in Tcl, Python, Perl or shell.
• Use AI coding assistants and agentic tools to speed up run analysis, debug, scripting and workflow automation, and share what works across the team. Review and validate all AI output before relying on it.
• Collaborate with RTL, circuit, integration, CAD and global engineering teams.

Skills

PnR

STA

Timing closure

SDC development

Physical design integration

Physical verification

Signoff

Low-power design

EM/IR

Tools

Fusion Compiler

Innovus

PrimeTime

Tempus

StarRC

Calibre

Job description

AMD Singapore hosts a design team delivering RTL/netlist-to-GDS flows, spanning floorplanning, power planning, placement, and timing convergence. You will work with AI-assisted workflows and modern EDA tools to accelerate delivery and ensure high-quality signoff.

The role focuses on owning blocks, subsystems, or integration efforts with a strong automation and AI-centric mindset, applying data-driven analysis and engineering judgment to validate results across RTL, CAD, and physical design teams.