Staff Silicon Design Engineer – Physical Design

Advanced Micro Devices, Inc.; Singapore; On-site; SGD 120,000 - 180,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD Singapore hosts a design team delivering RTL/netlist-to-GDS flows, spanning floorplanning, power planning, placement, and timing convergence. You will work with AI-assisted workflows and modern EDA tools to accelerate delivery and ensure high-quality signoff.

The role focuses on owning blocks, subsystems, or integration efforts with a strong automation and AI-centric mindset, applying data-driven analysis and engineering judgment to validate results across RTL, CAD, and physical design teams.

Qualifications

• Hands-on experience in one or more of: PnR, STA and timing closure, SDC development, physical design integration, physical verification and signoff, low-power design, EM/IR.
• Synopsys and/or Cadence tools, such as Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC or Calibre.
• Experience debugging complex design or flow problems.
• Advanced nodes and hierarchical designs are an advantage.
• Experience building reusable flows or methodologies is highly desirable.

Responsibilities

• Own or contribute to RTL/netlist-to-GDS implementation: floorplanning, power planning, placement, CTS, routing, optimization, ECOs and closure.
• Drive timing closure through STA, constraints (SDC) debugging, interface timing analysis and ECO development.
• Support hierarchical physical design and integration at block, subsystem and top level.
• Resolve challenges in timing, congestion, clocking, power, area, signal integrity and physical verification.
• Support signoff: STA, DRC/LVS, antenna, low-power checks and EM/IR.
• Build reusable automation in Tcl, Python, Perl or shell.
• Use AI coding assistants and agentic tools to speed up run analysis, debug, scripting and workflow automation, and share what works across the team. Review and validate all AI output before relying on it.
• Collaborate with RTL, circuit, integration, CAD and global engineering teams.

Skills

PnR

STA

Timing closure

SDC development

Physical design integration

Physical verification

Signoff

Low-power design

EM/IR

Tools

Fusion Compiler

Innovus

PrimeTime

Tempus

StarRC

Calibre

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believetechnology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMDis shapingthefuture.

Whetheryou’redesigning next-gen processors, enabling AI breakthroughs, orbringing leading edge products to market, every role at AMD contributes to something bigger— technologythat moves the world forward.Join us and, together, we’ll advance your career.

THE ROLE

Join our Singapore silicon design team across PnR, STA and physical design integration, supporting the full lifecycle from design handoff to timing convergence, physical verification and signoff. Depending on experience, you may own blocks, subsystems, STA or higher-level integration. AI-assisted and agentic workflows are central to how we work, and you'll use them with automation and modern EDA tools to accelerate delivery and improve quality.

THE PERSON

You enjoy solving complex physical design problems and understanding how logic, timing, physical implementation, power, verification and integration interact. You combine strong engineering fundamentals with an automation-first, AI-centric mindset, using scripting and AI-assisted techniques to analyze design data, improve workflows and build reusable solutions. You are data-driven, own problems from analysis through closure, and apply sound engineering judgment to independently validate everything AI produces.

KEY RESPONSIBILITIES

• Own or contribute to RTL/netlist-to-GDS implementation: floorplanning, power planning, placement, CTS, routing, optimization, ECOs and closure.
• Drive timing closure through STA, constraints (SDC) debugging, interface timing analysis and ECO development.
• Support hierarchical physical design and integration at block, subsystem and top level.
• Resolve challenges in timing, congestion, clocking, power, area, signal integrity and physical verification.
• Support signoff: STA, DRC/LVS, antenna, low-power checks and EM/IR.
• Build reusable automation in Tcl, Python, Perl or shell.
• Use AI coding assistants and agentic tools to speed up run analysis, debug, scripting and workflow automation, and share what works across the team. Review and validate all AI output before relying on it.
• Collaborate with RTL, circuit, integration, CAD and global engineering teams.

PREFERRED EXPERIENCE

• Hands-on experience in one or more of: PnR, STA and timing closure, SDC development, physical design integration, physical verification and signoff, low-power design, EM/IR.
• Synopsys and/or Cadence tools, such as Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC or Calibre.
• Experience debugging complex design or flow problems.
• Advanced nodes and hierarchical designs are an advantage.
• Experience building reusable flows or methodologies is highly desirable.

LOCATION

Singapore

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.