Senior RTL Design Engineer

AAC Technologies; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

AAC Technologies in Singapore seeks a Senior Digital IC Design Engineer with 7+ years of experience to lead mixed-signal subsystem design from implementation to silicon delivery.

You will work on IIC, I2S and SoundWire interfaces, RTL design, and high-level modelling for IP blocks. The role includes design reviews, timing and power analysis, and cross-functional silicon bring-up support.

Qualifications

• Bachelor or Master degree in Electrical and Electronic Engineering with 7+ years in digital CMOS IC design.
• Proficient in Verilog RTL design and high-level modelling for subsystem evaluation.
• Strong knowledge of IIC, I2S and SoundWire interface designs.

Responsibilities

• Mixed-signal subsystem design from implementation to chip-level delivery.
• Conduct micro-architectural studies for optimal hardware of IP blocks.
• Prepare design and verification reviews with technical staff.
• Perform logic synthesis, timing, and power analysis to optimize designs.
• Support pre-silicon verification and silicon bring-up with cross-functional teams.

Skills

Digital CMOS IC design

I2S interface design

IIC interface design

SoundWire interface design

Verilog RTL design

High-level modelling

Education

Bachelor or Master degree in Electrical & Electronic Engineering

Tools

Logic simulators

Waveform browsers

Power analysis tools

Spice co-simulation

Job description

JOB DESCRIPTION :

• Mixed-signal subsystem design from design implementation to final delivery for chip-level integration


• Perform micro-architectural studies to determine optimal hardware implementations of IP digital blocks to meet product requirements


• Ensure all required documentation are prepared according to the quality standards


• RTL logic design of modules using Verilog HDL. Designs may include power and clock management units, IIC, I2C, SoundWire digital interfaces, digital filters, etc


• Prepare and hold design and verification reviews with technical staff throughout project lifecycle


• Perform logic synthesis, timing and power analysis to optimise designs


• Pre-silicon verification utilizing various methodologies such as constrained random verification with block/subsystem/chip level UVM test benches, spice co-simulation of mixed signal blocks and FPGA emulation.


• Support Validation/bring-up of designs on silicon, providing support to cross-functional teams

JOB REQUIREMENTS :

• Bachelor or Master degree in Electrical and Electronic Engineering with minimum 7+ years of professional experience in digital CMOS IC design


• Experience using high-level modelling language/tool for designing and evaluating subsystems and algorithms


• Strong understanding of digital design, preferably in IIC, I2S, SoundWire interface design


• Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools, Verilog RTL design