Senior Process Engineer: SPC Analytics & Yield Optimization

Vanguard International Semiconductor Corporation; Singapore; On-site; SGD 70,000 - 120,000; Full time

Job summary

Vanguard International Semiconductor Corporation in Singapore seeks an experienced engineer to analyze SPC charts, perform DOE data analysis and drive yield improvements. You will coordinate with Equipment and Mfg.

teams to optimize process windows and ensure recipe/content compliance, while mentoring junior staff and maintaining TS16949 quality standards. The role requires strong leadership, deep analytical capability, and proficiency in JMP, Klarity ACE, PROMIS and RMS, with the ability to

Qualifications

• Min 5 years of wafer fabrication process experience.
• Experience with Thin Film CVD processes.
• Excellent teamwork and interpersonal, with strong written skills.
• Strong leadership to guide junior engineers.
• Strong analytical and logical thinking abilities.
• High integrity with leadership attributes.
• Proactive, accountable and able to work under pressure.
• Proficient in MS Office applications.

Responsibilities

• Analyse SPC charts, know PR rules and annotate to maintain quality troubleshooting rate for SPC OOC.
• Monitor critical SPC charts daily; perform process window study and suggest improvements to reduce OOC and boost CPK.
• Analyse split lot, DOE data, ET; sort yield using JMP and Klarity ACE.
• Create SPC charts, DCOP and modify SLDB using PROMIS (Si-View).
• Upload/check recipes to ensure recipe content compliance using RMS.
• Follow up on SPSR, MRB, 8D, TECN, or ECN spec updates.
• Setup and troubleshoot recipes/job files in all metrology tools within the Module.
• Provide pass-down support to troubleshoot process issues; establish CAS/procedures with cross-dept teams.
• Startup and qualify new processes and equipment; work with Equipment Engineer on acceptance; understand R&R concepts.
• Work to reduce process constraints for greater manufacturing flexibility.
• Perform process matching between equipment to reduce variation; use DOE to identify factors for better tool matching.
• Participate in CIP programs to optimize process window, cost, yield and productivity.
• Represent module in cross-functional teams to address yield excursions and engage in cross-fab benchmarking.
• Self-audit and update specifications/documentation to meet TS16949 Quality Standard requirements.
• Adhere to housekeeping and safety rules in office and FAB.
• Provide feedback/training to AEs or Techs on troubleshooting, process understanding, decision making and risk assessment.

Tools

JMP

Klarity ACE

PROMIS (Si-View)

RMS

MS Office

Job description

Vanguard International Semiconductor Corporation in Singapore seeks an experienced engineer to analyze SPC charts, perform DOE data analysis and drive yield improvements. You will coordinate with Equipment and Mfg.

teams to optimize process windows and ensure recipe/content compliance, while mentoring junior staff and maintaining TS16949 quality standards. The role requires strong leadership, deep analytical capability, and proficiency in JMP, Klarity ACE, PROMIS and RMS, with the ability to