Senior PVD Process Engineer: Yield & SPC Optimization

Vanguard International Semiconductor Corporation (VIS); Singapore; On-site; SGD 60,000 - 100,000; Full time

Job summary

Vanguard International Semiconductor Corporation (VIS) in Singapore seeks engineers to analyze SPC charts, perform data analyses, and monitor Cp/Cpk indices. You will work on split lots, DOE, and yield data using JMP and Klarity ACE, and create SPC charts and DCOP while modifying SLDB with PROMIS (Si-View).

The role includes ensuring recipe compliance via RMS, following ECN updates, and guiding junior engineers.

Qualifications

• Bachelor-level degree in engineering or science related field required.
• Minimum 2 years wafer fabrication process experience.
• Strong analytical and communication skills.
• Ability to work under pressure and own tasks.

Responsibilities

• Analyze SPC charts using SPACE and monitor Cp/Cpk indices.
• Lead improvement programs and coordinate cross‑department resolution.
• Collaborate with Equipment and Manufacturing teams to drive uptime and OEE.
• Lead small cross-functional teams to resolve yield excursions.
• Set up and troubleshoot recipes across metrology tools.
• Perform self-audits and update specifications to TS16949 standards.

Skills

Analytical thinking

Team player

Communication skills

Documentation/writing

Education

Electrical / Electronics / Microelectronics / Chemical Processing / Chemistry / Physics / Material Sciences / Mechanical

Tools

JMP

Klarity ACE

PROMIS (Si-View)

RMS

MS Office

Job description

Vanguard International Semiconductor Corporation (VIS) in Singapore seeks engineers to analyze SPC charts, perform data analyses, and monitor Cp/Cpk indices. You will work on split lots, DOE, and yield data using JMP and Klarity ACE, and create SPC charts and DCOP while modifying SLDB with PROMIS (Si-View).

The role includes ensuring recipe compliance via RMS, following ECN updates, and guiding junior engineers.