Senior Physical Design Engineer - Tapeout & Timing Expert

BITSILICA PTE. LTD.; Singapore; Sur place; SGD 78 000 - 100 000; Plein temps

Résumé du poste

BITSILICA PTE. LTD. in Singapore seeks a Physical Design Engineer with 4+ years experience to drive Netlist to GDSII. The role covers block to full-chip implementation, hierarchical partitioning, and high-performance core design across 3nm to 28nm nodes.

Responsibilities include timing signoff, power integrity, IR drop analysis, scan chain optimization, CTS, and clock tree constraint creation within ECO cycles. Collaboration with signoff teams is essential.

Qualifications

• Netlist to GDSII at block, subsystem, and full-chip levels.
• Multiple tapeouts on Netlist to GDSII.
• Block-level floorplanning and power planning.
• CTS/clock tree constraints creation for meeting specs.
• Timing closure in loop through STA and ECO cycles.

Connaissances

Block-level partitioning

Timing & ECO cycles

Power/IR drop analysis

Hierarchical floorplanning

Clock tree constraints

TCL scripting

Outils

Synopsys ICC/ICC2

Cadence Innovus

TCL scripting

Description du poste

BITSILICA PTE. LTD. in Singapore seeks a Physical Design Engineer with 4+ years experience to drive Netlist to GDSII. The role covers block to full-chip implementation, hierarchical partitioning, and high-performance core design across 3nm to 28nm nodes.

Responsibilities include timing signoff, power integrity, IR drop analysis, scan chain optimization, CTS, and clock tree constraint creation within ECO cycles. Collaboration with signoff teams is essential.