Physical Design Engineer

BITSILICA PTE. LTD.; Singapore; On-site; SGD 78,000 - 100,000; Full time

Job summary

BITSILICA PTE. LTD. in Singapore seeks a Physical Design Engineer with 4+ years experience to drive Netlist to GDSII. The role covers block to full-chip implementation, hierarchical partitioning, and high-performance core design across 3nm to 28nm nodes.

Responsibilities include timing signoff, power integrity, IR drop analysis, scan chain optimization, CTS, and clock tree constraint creation within ECO cycles. Collaboration with signoff teams is essential.

Qualifications

• Netlist to GDSII at block, subsystem, and full-chip levels.
• Multiple tapeouts on Netlist to GDSII.
• Block-level floorplanning and power planning.
• CTS/clock tree constraints creation for meeting specs.
• Timing closure in loop through STA and ECO cycles.

Skills

Block-level partitioning

Timing & ECO cycles

Power/IR drop analysis

Hierarchical floorplanning

Clock tree constraints

TCL scripting

Tools

Synopsys ICC/ICC2

Cadence Innovus

TCL scripting

Job description

Physical Design Engineer

Experience : 4+ Years

Salary Range :SGD 7000-9000

Skills & Technical Expertise Required:

• Netlist to GDSII at block level, Subsystem Level and at Full chip.
• Worked on multiple tapeouts on Netlist to GDSII
• Hierarchical partitioning and budgeting of block-level subsystems.
• Implementation of high performance (HP) cores, low power designs
• Node experience upto 3nm,7nm, 10nm, 14nm, 28nm.
• Timing Signoff in loop through STA and ECO cycle at block and at interface.
• Block level floor planning, power planning and IR drop analysis.
• Scan chain reordering / Scan Chain repartitioning
• CTS expertise and clock tree constraints creation for meeting specifications
• MMMC optimization at Block and Sub-System Level
• Timing closure with Crosstalk and AOCV / POCV
• TCL scripting to fundamentally understand tool usage.
• Mandatory EDA Skills
• PnR tools such as Synopsys ICC/ICC2 and/or Cadence Innovus