Senior Physical Design Engineer – SoC & PPA Mastery

LANCESOFT PTE. LTD.; Singapore; On-site; SGD 90,000 - 135,000; Full time

Job summary

LanceSoft PTE. LTD. in Singapore is seeking an experienced IC design engineer to own end-to-end physical design for complex SoCs/IP blocks from RTL handoff to GDSII. You will define floorplanning, CTS, placement, routing, and timing closure strategies to optimize power, performance, and area.

Collaborate with RTL, DFT, verification, and packaging teams; drive EDA tool flow automation and mentor junior engineers to sustain design excellence and tape-out readiness.

Qualifications

• Experience in end-to-end physical design of complex SoCs/IP blocks.
• Ability to define and drive floorplanning, CTS, placement and routing strategies.
• Proven track record in achieving timing closure and PPA optimization.
• Experience with design constraints, synthesis strategies and sign-off criteria.
• Strong collaboration with RTL, DFT, verification and packaging teams.

Responsibilities

• Execute end-to-end physical design flow from RTL handoff to GDSII.
• Define and drive floorplanning, CTS, placement, routing, and timing closure.
• Own and optimize power, performance, and area (PPA) metrics.
• Manage constraints, synthesis strategies, and sign-off criteria.
• Collaborate with front-end RTL, DFT, verification, and packaging teams.
• Drive EDA tool flow automation and methodology improvements.
• Mentor junior engineers and promote design excellence.
• Work with foundries and vendors on process technology bring-up and tape-out readiness.

Skills

Physical design

Floorplanning

CTS

Placement

Routing

Timing closure

PPA optimization

Constraints

Synthesis

Sign-off

Mentoring

EDA automation

Cross-functional collaboration

Vendor interaction

Education

Tools

EDA tools

Job description

LanceSoft PTE. LTD. in Singapore is seeking an experienced IC design engineer to own end-to-end physical design for complex SoCs/IP blocks from RTL handoff to GDSII. You will define floorplanning, CTS, placement, routing, and timing closure strategies to optimize power, performance, and area.

Collaborate with RTL, DFT, verification, and packaging teams; drive EDA tool flow automation and mentor junior engineers to sustain design excellence and tape-out readiness.