Senior SoC Physical Design Engineer - Shape Next-Gen Silicon

SILICON LABORATORIES INTERNATIONAL PTE. LTD.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Benefits offered by this job

Medical Insurance

Dental Coverage

Office near Tai Seng MRT

Job summary

SILICON LABORATORIES INTERNATIONAL PTE. LTD. is seeking a Design Engineer to drive the physical design of complex SoCs, covering synthesis, floorplanning, place-and-route and sign-off flows. You will optimise power, performance and area while ensuring robust timing closure.

Collaborate with RTL, DFT, verification and packaging teams; lead EDA tool flow improvements and mentor junior engineers. Office location is in Singapore, with opportunities to work with foundries on process readiness.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 4+ years of ASIC physical design experience.
• Hands-on experience with Synopsys and Cadence tool suites.
• Strong timing analysis, low-power methods and ECO flows.
• Knowledge of architecture-to-GDSII flows and sign-off requirements.

Responsibilities

• Drive end-to-end physical design flow for complex SoCs and IPs.
• Define floorplanning, CTS, placement, routing and timing closure strategies.
• Own power, performance and area metrics for assigned designs.
• Manage constraints, synthesis strategies and sign-off criteria.
• Collaborate with RTL, DFT, verification and packaging teams.
• Advance EDA tool flow automation and methodology improvements.
• Mentor and guide junior engineers in design excellence.
• Coordinate with foundries and vendors on process bring-up and tape-out readiness.

Skills

End-to-end physical design flow

Floorplanning

Clock-tree synthesis

Placement and routing

Timing closure

Power optimization

PPA optimization

DFT familiarity

Team mentorship

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

4+ years of ASIC physical design experience

Tools

Synopsys ICC2

Fusion Compiler

PrimeTime

Cadence Innovus

Tempus

DFT tools

Job description

SILICON LABORATORIES INTERNATIONAL PTE. LTD. is seeking a Design Engineer to drive the physical design of complex SoCs, covering synthesis, floorplanning, place-and-route and sign-off flows. You will optimise power, performance and area while ensuring robust timing closure.

Collaborate with RTL, DFT, verification and packaging teams; lead EDA tool flow improvements and mentor junior engineers. Office location is in Singapore, with opportunities to work with foundries on process readiness.