Senior PCIe IP RTL Engineer — Design & Verification

Bitdeer Group; Singapore; On-site; SGD 70,000 - 100,000; Full time

Benefits offered by this job

Attractive welfare benefits

Training and mentoring opportunities

Inclusive work environment

Job summary

Bitdeer Group in Singapore is looking for an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe-related IP blocks. This role involves ensuring functional coverage, contributing to both pre-silicon and post-silicon debug activities, and collaborating with various teams to deliver high-quality IP solutions.

The ideal candidate will have at least 5 years of experience in semiconductor R&D, a strong understanding of PCIe architecture, and the ability to work with scripting languages like Perl and Shell.

Qualifications

• 5+ years in semiconductor or high technology R&D experience.
• Experience with industry-standard tools in an SoC/IP environment.
• Strong understanding of PCIe architecture.

Responsibilities

• Implement Verilog RTL for PCIe-related IP blocks.
• Ensure 100% functional coverage in verification.
• Support software development and debugging.

Skills

Verilog RTL development

Problem-solving skills

Scripting languages (Perl, Shell, TCL)

PCIe architecture understanding

Education

Master’s degree or Bachelor’s in Electrical or Computer Engineering

Job description

Bitdeer Group in Singapore is looking for an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe-related IP blocks. This role involves ensuring functional coverage, contributing to both pre-silicon and post-silicon debug activities, and collaborating with various teams to deliver high-quality IP solutions.

The ideal candidate will have at least 5 years of experience in semiconductor R&D, a strong understanding of PCIe architecture, and the ability to work with scripting languages like Perl and Shell.