Senior NAND Cell Device Engineer – 3D NAND Innovation

Micron Technology, Inc.; Singapore; On-site; SGD 140,000 - 190,000; Full time

Job summary

Micron Technology, Inc. in Singapore is seeking a Senior/Principal Engineer to perform electrical characterization of 3D NAND memory cells and develop novel device solutions for next-generation non-volatile memory technologies.

You will work with process, integration, product, and design teams to identify improvement opportunities, refine specifications, and address circuitry and array challenges in a collaborative R&D environment.

Qualifications

• MS/PhD in Electrical Engineering, Physics, Materials Science or a related field.
• Strong foundation in semiconductor device physics and fabrication processes.
• Experience with data analysis and scripting tools such as Python, JMP/JSL, or Perl.

Responsibilities

• Characterize NAND memory cell and array behavior to identify device improvement opportunities.
• Develop understanding of performance and reliability requirements for new NAND cells and help refine specifications.
• Analyze automated tester data to identify qualification gaps, new device corners, and screening improvements.
• Contribute to NAND cell architecture and process definition through device physics and array operation expertise.
• Collaborate with process, integration, product, and design teams to address cell challenges and deliver improvement roadmaps.

Skills

Device physics

Semiconductor fabrication

Data analysis

Python

JMP/JSL

Perl

Communication

Education

MS/PhD in Electrical Engineering, Physics, or Materials Science

Tools

Python

JMP/JSL

Perl

Job description

Micron Technology, Inc. in Singapore is seeking a Senior/Principal Engineer to perform electrical characterization of 3D NAND memory cells and develop novel device solutions for next-generation non-volatile memory technologies.

You will work with process, integration, product, and design teams to identify improvement opportunities, refine specifications, and address circuitry and array challenges in a collaborative R&D environment.