Senior IC Designer – High-Speed Analog & CMOS Layout

ASTERA LABS SINGAPORE PRIVATE LIMITED

Singapore

On-site

SGD 90,000 - 120,000

Full time

14 days+

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Job summary

ASTERA LABS SINGAPORE PRIVATE LIMITED seeks a motivated Integrated Circuit Designer to collaborate with layout and design engineers across multiple time zones. You will design and develop IC layouts for advanced CMOS nodes, focusing on minimizing parasitics and meeting tight DRC/LVS constraints.

Your role includes managing manufacturing processes, developing test procedures, and advising on process technology while maintaining equipment.

Qualifications

Bachelor’s degree in electrical engineering is required.
2+ years of experience in layouts for high-speed analog IC designs in finFET technology.
Experience with layout extraction tools and analyzing layout parasitics to achieve high-quality layout for high-speed circuits.
EMIR and antenna DRC rules aware layout practices.
Experience writing SKILL and TCL scripts is recommended.

Responsibilities

Design and develop the layout for ICs using floor planning and building blocks.
Manage manufacturing process including technology yield and performance.
Develop test programmes and procedures to ensure product performance.
Advise on semiconductor process technology and maintain/repair process equipment.