Senior IC Design Engineer - AI-Driven Physical

AUREXIS TECH PTE. LTD.; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

AUREXIS TECH PTE. LTD. is seeking an engineer to perform RTL-to-GDS physical implementation for ASIC IP, subsystem, and SoC designs using leading EDA tools and AI-assisted methodologies.

You will develop synthesis, DFT, and timing closure strategies, ensuring DRC/LVS, STA, and GDS tape-out verification. Collaboration across teams will target strong PPA and timing goals, with scripting in Tcl/Python/Perl and experience in Verilog/SystemVerilog/C/C++.

Qualifications

• Bachelor/Master degree in Electronics/Electrical/Computer Engineering or related field.
• 1+ year of relevant experience in RTL-to-GDS physical design.
• Experience with RTL-to-GDS physical design flow including synthesis, floorplanning, placement, CTS, routing, and timing closure.
• Knowledge of STA, DRC/LVS, physical verification and design optimization.
• Experience with AI-assisted workflows and LLMs to automate scripts and documentation.
• Proficiency in Tcl, Python, Perl, Shell, Makefile, Verilog, SystemVerilog, C/C++.
• Familiarity with AI-assisted backend EDA tools (Synopsys, Cadence) is preferred.

Responsibilities

• Perform RTL-to-GDS physical implementation for ASIC IP/subsystem/SoC designs using industry-leading EDA tools and AI-assisted methodologies.
• Develop and execute synthesis, DFT, and timing closure strategies, including DRC/LVS, STA, scan/DFT validation, and GDS tape-out verification with AI-assisted methodologies.
• Collaborate with cross-functional teams to achieve power, performance, area (PPA) and timing goals.
• Design, implement, and maintain synthesis, DFT, and STA scripts to improve automation, flow robustness, and design quality.
• Leverage AI/LLM tools to automate workflows, accelerate analysis, optimize PnR and timing prediction, and generate design constraints.

Job description

AUREXIS TECH PTE. LTD. is seeking an engineer to perform RTL-to-GDS physical implementation for ASIC IP, subsystem, and SoC designs using leading EDA tools and AI-assisted methodologies.

You will develop synthesis, DFT, and timing closure strategies, ensuring DRC/LVS, STA, and GDS tape-out verification. Collaboration across teams will target strong PPA and timing goals, with scripting in Tcl/Python/Perl and experience in Verilog/SystemVerilog/C/C++.