Senior Hybrid Bonding Process Engineer

Applied Materials, Inc.; Singapore; On-site; SGD 90,000 - 140,000; Full time

Job summary

Applied Materials, Inc. is seeking a Process Engineer in Singapore to lead development and integration of Hybrid Bonding technologies for logic, memory, and 3D heterogeneous integration.

You will design, optimize, and qualify end-to-end processes, and collaborate with R&D teams and customers to push state-of-the-art packaging solutions. The role requires 5+ years in semiconductor technology development and hands-on DOE/statistical analysis.

Qualifications

• Bachelor’s, Master’s, or PhD in Engineering, Materials Science, Physics, or related disciplines.
• Minimum 5 years of semiconductor experience in technology development, process integration, or advanced packaging.
• Hands-on experience in Hybrid Bonding, DOE, JMP/Minitab, reliability, metrology is preferred.

Responsibilities

• Develop and optimize end-to-end Hybrid Bonding processes, including wafer/die surface preparation, wet and dry cleaning, plasma activation, dielectric-to-dielectric bonding, Cu-Cu direct bonding, and post-bond annealing to achieve bonding yield, alignment, electrical performance, and reliability targets.
• Design and execute process characterization and DOE studies to establish process windows, understand bonding mechanisms, and improve critical metrics such as bond strength, void density, overlay accuracy, Cu oxidation control, and interface quality.
• Investigate and resolve process integration challenges related to CMP surface topography, surface chemistry, contamination control, pattern density effects, thermal budget, wafer / die warpage, and bonding defectivity through data-driven root cause analysis.
• Collaborate with equipment, materials, metrology, and integration teams to develop scalable solutions for die-to-wafer (D2W) Hybrid Bonding applications supporting HBM, Logic, and 3D heterogeneous integration technologies.
• Define and implement characterization methodologies using optical inspection, IR imaging, SEM, AFM, XPS, contact angle measurement, electrical test, and reliability evaluation to monitor process performance and qualify new technologies.
• Support development of advanced packaging technologies including HBM, Logic, TSV, RDL, and die-to-wafer bonding.
• Engage customers, research institutes, and ecosystem partners on joint technology development projects.
• Generate technical reports, patents, publications, and technology roadmaps.

Skills

Hybrid Bonding knowledge

DOE statistical analysis

Education

Bachelor’s / Master’s / PhD in Engineering, Materials Science, Physics

Tools

DOE

JMP

Minitab

Job description

Applied Materials, Inc. is seeking a Process Engineer in Singapore to lead development and integration of Hybrid Bonding technologies for logic, memory, and 3D heterogeneous integration.

You will design, optimize, and qualify end-to-end processes, and collaborate with R&D teams and customers to push state-of-the-art packaging solutions. The role requires 5+ years in semiconductor technology development and hands-on DOE/statistical analysis.