Advanced Packaging Process Engineer

Applied Materials, Inc.; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Applied Materials, Inc. is seeking a Process Engineer with a strong layout design background. You will own test-vehicle design for hybrid bonding development, create GDS layouts, and validate interconnect performance from mask to measured data.

Collaborate with process, metrology, and integration teams to analyze bond quality, reliability, and interface defects, while supporting D2W and W2W bonding flows and deriving layout rules from process requirements.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, or related field.
• 3+ years of IC or package layout experience with hands-on GDSII/OASIS work.
• Solid understanding of electrical test structures and how to design them for meaningful, measurable results.
• Working knowledge of BEOL metallization, CMP, and dielectrics.

Responsibilities

• Design and layout test vehicles and chips for hybrid bonding and advanced packaging from floorplan to GDSII/OASIS tape-out.
• Develop parameterized test structures and automation to support layout variants and testing.
• Run DRC/LVS checks and coordinate with mask shops and fabs for mask generation and qualification.
• Analyze electrical data and correlate results to process conditions and layout variables; present findings.

Skills

IC/package layout

GDSII/OASIS experience

Electrical data analysis

Test structure knowledge

Education

Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, or related field

Tools

Cadence Virtuoso

KLayout

Calibre

Job description

Who We Are

Applied Materials is the global leader in materials science and engineering solutions that are at the foundation of virtually every new semiconductor chip and advanced display in the world. The equipment that we create and service is essential to advancing AI and accelerating the commercialization of next-generation semiconductor chips. Join us and push the boundaries of materials science and engineering in a company at the foundation of the electronics industry. The work we do together advances the world’s technology.

What We Offer

Location: Singapore,SGP

You’ll benefit from a supportive work culture that encourages you to learn, develop, and grow your career as you take on challenges and drive innovative solutions for our customers. We empower our team to push the boundaries of what is possible—while learning every day in a supportive leading global company. Visit our Careers website to learn more.

At Applied Materials, we care about the health and wellbeing of our employees. We’re committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits.

As a Process Engineer, you'll play a crucial role in designing and optimizing manufacturing processes for display and semiconductor manufacturing technologies. You will collect and analyze data, perform hardware characterization, and troubleshoot engineering issues. You'll also measure film properties, generate technical documentation, and engage with customers to resolve concerns. Process Engineers collaborate with vendors and suppliers, and become familiar with implementing new technologies and products. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects.

About the Role

We are looking for an engineer with a strong layout design background to own the design of test vehicles for advanced packaging development, with a focus on die-to-wafer (D2W) hybrid bonding. You will create the GDS layouts and electrical test structures that let us characterize interconnect performance, and work hands-on with the process team to develop, debug, and qualify the hybrid bonding flow. This role sits at the intersection of design, process, and electrical characterization, and suits someone who enjoys seeing a layout through from mask to measured data.

Key Responsibilities

Test vehicle design and layout

• Design and lay out test vehicles and test chips for hybrid bonding and advanced packaging process development, from floorplan through final GDSII/OASIS tape-out.
• Create and maintain parameterized test structures, including Kelvin (4-terminal) structures for single-interconnect resistance, daisy chains for yield and continuity, comb and serpentine structures for leakage and shorts, and related structures such as cross-bridge Kelvin resistors and alignment/overlay marks.
• Run DRC and LVS checks, manage layer maps and design rules, and coordinate with mask shops and foundry or internal fab teams for mask generation.
• Develop scripts or PCells (e.g. Python/KLayout, SKILL, or similar) to automate structure generation and design variants.

Hybrid bonding process support

• Support D2W hybrid bonding process development, including surface preparation, CMP and dishing control, plasma activation, die placement and alignment, bonding, and post-bond anneal.
• Translate process requirements (pad pitch, Cu density, dummy fill, bonding pad recess) into layout rules and test vehicle designs.
• Work with process, metrology, and integration teams to analyze bond quality, alignment accuracy, voids, and interface defects (e.g. SAM/CSAM, IR, SEM/TEM cross-sections).

Electrical test and data analysis

• Define test plans and probe-card or pad layouts for the structures you design.
• Analyze electrical data (interconnect resistance, yield, leakage, breakdown) and correlate results to process conditions and layout variables.
• Support reliability evaluation such as thermal cycling, high-temperature storage, and electromigration on daisy chain vehicles.
• Present findings and recommendations to cross-functional teams and customers.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, or a related field.
• 3+ years of experience in IC or package layout, with hands-on GDSII/OASIS work using tools such as Cadence Virtuoso, KLayout, Calibre, or equivalent.
• Solid understanding of electrical test structures (Kelvin, daisy chain, comb/serpentine leakage) and how to design them for meaningful, measurable results.
• Working knowledge of semiconductor process flows, especially back-end-of-line (BEOL) metallization, CMP, and dielectrics.
• Ability to analyze electrical data and connect it to layout and process root causes.

Preferred Qualifications

• Direct experience with hybrid bonding (D2W or W2W), Cu-Cu/dielectric bonding, or other advanced packaging (micro-bumps, TSV, fan-out, 2.5D/3D integration).
• Scripting experience (Python, SKILL, Tcl) for layout automation and data analysis.
• Familiarity with bonding and metrology equipment, such as die bonders, plasma activation tools, CMP, CSAM, and overlay metrology.
• Experience with design-for-test, probe card design, or parametric test systems.
• Knowledge of reliability testing standards (JEDEC) for packaging.

What We Value

Strong ownership, clear communication across design and process teams, comfort working in a fast-moving R&D environment, and attention to detail at both the layout and the data level.

Additional Information

Time Type:

Full time

Employee Type:

Assignee / Regular

Travel:

No

Relocation Eligible:

Yes

Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.