Senior Engineer, FPGA

Ethos Search Associates Pte Ltd; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Ethos Search Associates Pte Ltd seeks a Senior FPGA Engineer to drive FPGA image development for pre-silicon prototyping environments. You will collaborate with SoC design, software development, design verification, and system test teams to deliver robust FPGA images.

Required experience includes RTL design, verification, and FPGA prototyping, with strong skills in timing constraints, debugging RTL, and HDL toolchains. This role focuses on pre-silicon efforts and hands-on lab bring-up.

Qualifications

• BSEE or BSCE with 6+ years of SoC design, verification, or related work experience and 8+ years of FPGA design, bring-up, debugging, and verification.
• Strong experience with top-down FPGA development process and FPGA-based prototyping on FPGA development platforms.
• Solid experience defining timing constraints for Static Timing Analysis and familiarity with Cadence SoC flow.
• Expertise in Intel Quartus Prime Pro and Xilinx Vivado suites and RTL-to-bitstream flow.
• Some familiarity with C language programming and source control systems (git).
• Hands-on lab bring-up experience, debugging, and instrument usage.

Responsibilities

• Implement and debug FPGA designs on AMD FPGA prototyping platforms using Xilinx Vivado and ISE tools.
• Implement and debug FPGA designs on Stratix-10 development boards using Intel Quartus Prime Pro.
• Support a regression test-suite of system-level tests to validate updated FPGA builds.
• Assist development teams in reproduction, triage, and debugging of issues pre- and post-silicon.
• Define and implement timing constraints for the FPGA development flow.

Skills

FPGA design

RTL design

verification

debugging

C language

Git

lab bring-up

Python

Education

BSEE/BSCE

Tools

Xilinx Vivado

Xilinx ISE

Intel Quartus Prime Pro

Cadence SoC flow

Git

Simulation tools

Job description

As the Senior Engineer, FPGA, you will drive thedevelopment andrenderingof FPGA images in support of our pre-silicon prototypingenvironments.

Inthis role, youwill workwith ourSoC design,softwaredevelopment,designverification, and system test teams as our primary internal customersfor the FPGA images.

The successful candidatewill haveexperience in RTL design, verification, and FPGA/Prototyping platform creation to support Design Verification, Validation, Software Development and System Test at the pre-silicon phase.

The person in this rolemust becomfortable working with RTL to implement specialized changes to the SoC database for the FPGA developmentflow. Thisrole will require defining and implementing internal and externalFPGAtiming constraints to enable repeated delivery of design iterations to the software and validation teams.The candidatewillbe requiredtodebug RTLdesignsusing FPGA tools, external logic analyzers, and protocol analyzers.

Responsibilities

• ImplementanddebugFPGAdesignsonAMD FPGAbasedprototypingplatformsusingXilinxVivadoandISEtools.
• ImplementanddebugFPGAdesignsona Stratix-10developmentboardusingIntelQuartusprimePro.
• Support a regression test-suite consisting of system-level test cases tovalidateupdated FPGA builds.
• Assistdevelopmentteamsinreproduction,triage,anddebugofissuesbothpre-siliconandpost-silicon
• Define and implement timing constraints.

Qualifications

• BSEE or BSCE with6+ years of SoC design, verification, or related work experience and 8+ years of experienceofFPGA design, bring-up, debugging, and verification.
• In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on an FPGA development platform.
• Solid experience withdefiningtiming constraintsfor Static Timing Analysis.
• Some familiarity with Cadence SoC design flow.
• Expertisein both Intel Quartus Prime Pro and XilinxVivadosuites.
• Solid understanding of the tool flow from RTL to bitstream.
• Some familiarity with programming inC language.
• Familiarity with source code control systems (git)required.
• Familiarity with simulation tools.
• Hands-onlabbring-up experience, debug, and instrument usage.

In addition, the following areas of experience are highly desirable for the position but not strictlyrequired:

• In-depth experience with Stratix 10 FPGA platforms: boards,debug, performance, and throughput tuning.
• In-depth experience with AMD VU19P prototyping systems, debug, designpartitioning, performance, and throughput tuning.
• Experience with SiemensproFPGAprototyping/emulation platform and VPS software.
• Experience with ARM's MPS4 platform.
• Experience with low power designs.
• Experience with embedded microprocessors.
• Proven design validation skills.
• In-depth experience writing Verilog code.
• Experience with System Verilog verification environments.
• Good analytical skills.
• Python experience.
• YAML
• Peripheral protocols: I2C, I3C, MSPI, UART, USB