Senior FPGA Prototyping & SoC Engineer

SEARCH STAFFING SERVICES PTE. LTD; Singapore; On-site; SGD 120,000 - 180,000; Full time

Job summary

Senior FPGA Engineer in Singapore to support SoC pre-silicon prototyping with FPGA images for internal teams. Responsibilities include prototyping, RTL implementation, timing optimization, debugging, and cross-functional collaboration to deliver repeatable FPGA builds across SoC iterations.

The role requires 8+ years in FPGA design/embedded development and proficiency with Verilog/SystemVerilog, Vivado/Quartus, and peripheral protocols. Local candidates preferred.

Qualifications

• Strong FPGA experience with hands-on design, prototyping, bring-up and debugging.
• RTL/Verilog flow from RTL through synthesis, place-and-route and bitstream generation.
• Experience with FPGA prototyping platforms and board bring-up, performance tuning.

Responsibilities

• FPGA Prototyping & Development – develop, implement and bring up FPGA images for SoC pre-silicon prototyping.
• RTL & FPGA Implementation – modify and debug RTL for FPGA implementation from RTL to bitstream.
• Timing & Performance Optimization – define timing constraints and optimize for performance, throughput and resource usage.
• Hands-on Debug & Validation – debug FPGA and RTL issues using debugging tools and analyzers.
• Cross-Functional SoC Support – collaborate with SoC Design, Verification, Software and System Test teams.

Skills

FPGA design

RTL/Verilog

FPGA prototyping

Timing analysis

SystemVerilog

Python

Education

BSEE/BSCE or related degree

Tools

Xilinx Vivado

Intel Quartus Prime Pro

Oscilloscopes

Logic analyzers

Job description

Senior FPGA Engineer in Singapore to support SoC pre-silicon prototyping with FPGA images for internal teams. Responsibilities include prototyping, RTL implementation, timing optimization, debugging, and cross-functional collaboration to deliver repeatable FPGA builds across SoC iterations.

The role requires 8+ years in FPGA design/embedded development and proficiency with Verilog/SystemVerilog, Vivado/Quartus, and peripheral protocols. Local candidates preferred.