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Nanyang Technological University’s Centre of Hardware Assurance (CHA) on the PACE team invites a senior researcher to advance hardware security for embedded systems. You will evaluate MCUs, implement PQC and QKD, and develop robust security architectures for silicon trust.
Role emphasizes rigorous experimentation, data analysis, and dissemination of findings through top conferences and journals, with opportunities to shape a long-term hardware-forensics roadmap.
About the Centre of Hardware Assurance (CHA) The vision of Centre of Hardware Assurance (CHA) is to be the National Centre of Excellence for Hardware Assurance. The mission of CHA is to provide analysis capabilitiesfrom non-invasive to invasive techniques in vulnerability assessment, forensics and certification of hardware devices and components. CHA comprises three main research groups: the Hardware Analysis team (HA), Circuit Analysis (CA) team, and Physical Analysis & Cryptographic Engineering (PACE) team. The HA team focuses on developing new techniques using state-of-the‑art failure analysis tools for package and chip access, imaging and security assessment. TheCA team researchesthe design and development of advanced algorithms and tools for automatic and efficient analysis of VLSI digital integrated circuits, utilizing deep learning techniques for better adaptability and productivity. The PACE team aims to advance side‑channel and fault analysis techniques for hardware security analysis.
Key Purpose of the RoleTechnological infrastructure and silicon chips are foundational to a nation’s economy and security. The proliferation of hardware IP and IoT—including vehicle networking, smart grids, and medical devices—has introduced complex security vulnerabilities. Integrated circuits, FPGAs, and non‑volatile memories face increasing threats from malicious actors. Ensuring the security of these systems is critical.
Hardware security establishes trust and authenticity through secure design, access control, and communication. This role addresses these challenges by securing embedded systems against classical attacks and emerging quantum threats. You will evaluate and implement security architectures, including future‑proof Post‑Quantum Cryptography (PQC) and Quantum Key Distribution (QKD), to ensure cryptographic agility within silicon. This work aims to protect critical infrastructure from future decryption risks and maintain a robust hardware root of trust.
We regret that only shortlisted candidates will be notified.