Research Fellow (IC Designer)

National University of Singapore; Singapore; On-site; SGD 70,000 - 110,000; Full time

Job summary

National University of Singapore invites applications for a Research Fellow (IC Designer) in the Electrical and Computer Engineering department. The role focuses on advanced modeling, predictive power management and integration of circuits, models and runtime adaptation, with opportunities to publish at top conferences.

The appointment is a 1-year contract with possible extension, salary commensurate with qualifications and experience. Immediate start is possible at Kent Ridge Campus.

Qualifications

• PhD in Electrical Engineering or related field required.
• Knowledge of circuit architectures and transistor-level design.
• Knowledge of silicon chip design and EDA tools.
• Ability to work independently and in a team.
• Strong communication and interpersonal skills.
• Open to fixed-term contract.

Responsibilities

• Modeling of physical, thermal and circuit-to-system aspects.
• High-level exploration and modeling for power management.
• Predictive power management from circuits to model optimization and test chip demo.
• Predictive power management with voltage/temperature-aware optimization and demos.
• Runtime adaptation for accurate event detection with test chip demo.
• Integrate voltage/temperature-aware circuits, models and runtime adaptation.
• Author high-quality research papers and present findings internationally.
• Manage project milestones and guide PhD and master’s students.

Skills

Independence

Team collaboration

Communication skills

Fixed-term contract

Education

PhD in Electrical Engineering

Tools

EDA tools

Silicon chip design

Job description

Job Title: Research Fellow (IC Designer)

University-Level Unit: College of Design and Engineering

Faculty/Department-Level Unit: Electrical and Computer Engineering

Employee Category: Research Staff

Location_ONB: Kent Ridge Campus

Posting Start Date: 22/06/2026

Job Description

We are looking for a Research Fellow for the (SHINE) Centre 2.0 co-led by Professor Massimo Alioto, at the Department of Electrical and Computer Engineering, National University of Singapore (NUS).

The Selected Candidate Is Expected To Work On

• physical, thermal and circuit-to-system modeling, design exploration, architecture and validation/testing framework
• high-level exploration and modeling for predictive power management
• predictive power management from circuits to voltage-aware model optimization and test chip demonstration
• predictive power management from circuits to voltage and temperature-aware model optimization and test chip demonstration
• predictive power management runtime adaptation for accurate event detection with test chip demonstration
• full integration of voltage/temperature-aware circuits, models and runtime adaptation for accurate event detection
• authoring high-quality research papers for leading conferences and journals and presenting findings at international conferences.
• managing technical milestones for the project and providing technical guidance to PhD and master’s students within the group.

The appointment can commence immediately with a 1-year contract, with prospect of extension. Salary will be commensurate with qualifications and experience.

Qualifications

The candidate must possess:

• A PhD degree in either Electrical Engineering or strictly related (e.g., Computer, Electronics, Communication, or Information Engineering).
• Knowledge on circuit architectures, transistor-level design.
• Knowledge on silicon chip design, EDA tools.
• Ability to work independently and collaboratively in a team environment.
• Good communication and interpersonal skills.
• Open to fixed term contract.