Research Fellow (CNT CMOS Process Development and Device Integration)

National University of Singapore; Singapore; On-site; SGD 60,000 - 90,000; Full time

Job summary

The National University of Singapore's Department of Electrical and Computer Engineering seeks a Research Fellow to lead wafer-scale CNFET CMOS process development and device fabrication. The role interfaces with industry partners to transfer a documented process to production.

You will qualify CNT array films, characterize devices electrically, and author the process-of-record, including flow sheets and metrology plans, enabling lab-to-fab transfer.

Qualifications

• Job requires leadership in research, fabrication and process development for CNFET CMOS technology.
• Experience with device characterization and integrating lab processes into production lines is expected.

Responsibilities

• Develop and optimise CNFET core process modules (ALD high-k gate stacks, source/drain metallisation, channel cleaning, passivation, threshold control).
• Scale device geometry using electron-beam or DUV lithography on production-compatible lines.
• Qualify CNT array films for device-grade channels (density, alignment, purity) with SEM, AFM, Raman, and optical mapping.
• Electrically and statistically characterize devices (transfer/ output, contact resistance, subthreshold swing, hysteresis, reliability).
• Author the process-of-record (flow sheet, recipes, metrology plan, inline controls) for lab-to-fab transfer.

Job description

Company description

The National University of Singapore is the national research university of Singapore. Founded in 1905 as the Straits Settlements and the Federated Malay States Government Medical School, NUS is the oldest higher education institution in Singapore

Job Description

The Department of Electrical and Computer Engineering (ECE), College of Design and Engineering, is seeking a Research Fellow to lead the process development and device fabrication track of a research programme on wafer-scale carbon nanotube CMOS. The work runs on two tracks: process modules are developed and optimised on coupon-scale samples at NUS, then transferred as a documented process-of-record to an industry partner for verification on a 200 mm line.

Key responsibilities:

• Develop and optimise the core CNFET process modules — ALD high-k gate stacks, source/drain contact metallisation, channel cleaning and passivation, and threshold-voltage control — within a BEOL-compatible (≤ 400 °C) thermal budget.
• Build a silicon-fab-compatible contact integration scheme using only unit processes a production line already runs, and scale the device geometry to aggressive contacted gate pitch by electron-beam or DUV lithography.
• Qualify incoming carbon nanotube array film as a device-grade channel material (density, alignment, uniformity, purity, residues) by SEM, AFM, Raman and optical mapping, and define acceptance criteria.
• Characterise devices electrically and statistically — transfer and output characteristics, contact resistance, subthreshold swing, hysteresis, threshold distributions and basic reliability screening.
• Author the process-of-record (flow sheet, recipes, metrology plan, in-line control limits) and support its lab-to-fab transfer to the partner line, including joint failure analysis and corrective process splits.