Research Fellow: CNFET Logic & Emerging Memory IC Design

National University of Singapore; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

The National University of Singapore’s Department of Electrical and Computer Engineering invites applications for a Research Fellow to lead the CNFET logic and circuit design track within a nanoelectronics project. You will develop CNFET digital circuits, standard cells, and Verilog-A models from measurement data.

You will design memory macros, evaluate device–circuit co-design, explore monolithic 3D integration, coordinate tape-outs with process partners, publish results, and mentor graduate

Qualifications

• PhD in Electrical Engineering, Microelectronics, Computer Engineering or a closely related field (awarded, or thesis submitted, at the time of application).
• Demonstrated digital and/or mixed-signal IC design experience using a commercial design flow (Cadence Virtuoso and Spectre, synthesis and place-and-route), including full-custom layout with DRC/LVS closure.
• Experience designing memory macros and their peripheral circuits — sense amplifiers, write drivers, decoders and timing control — for SRAM, DRAM, gain cell or emerging memory.
• Compact modelling and device-circuit co-design, including Verilog-A model development and parameter extraction from measured data.
• Statistical and Monte Carlo circuit analysis, and the ability to reason about variability and yield when the technology has no mature PDK.
• Scripting for design automation and data analysis (Python, TCL, SKILL or equivalent).
• A publication record commensurate with career stage, strong written and spoken English, and the ability to work independently and to guide junior researchers.

Responsibilities

• Design CNFET digital circuits and standard cells, and build and calibrate CNFET compact models (Verilog-A) against measured device data.
• Design memory macros in emerging memory technologies — including gain cell, oxide-semiconductor based and resistive (RRAM) memories — covering the array and its peripheral circuits (sense amplifiers, write drivers, decoders and drivers, timing and refresh control).
• Carry out device-circuit co-optimisation and variation-aware, defect-tolerant design for immature technologies, and benchmark power, performance and area against silicon CMOS.
• Explore monolithic 3D integration enabled by the low-temperature (BEOL-compatible) flows — memory over logic, and compute-in-memory / edge-AI applications.
• Produce test-vehicle layouts with DRC/LVS closure, coordinate tape-out with the process team and industry partners, and lead the electrical testing and analysis of fabricated chips.
• Publish in leading venues, supervise graduate students, and contribute to invention disclosures and research proposals.

Skills

Digital IC design

Memory macro design

Verilog-A modelling

Scripting (Python)

English communication

Education

PhD in Electrical Engineering or related

Tools

Cadence Virtuoso

Cadence Spectre

Place-and-Route

Job description

The National University of Singapore’s Department of Electrical and Computer Engineering invites applications for a Research Fellow to lead the CNFET logic and circuit design track within a nanoelectronics project. You will develop CNFET digital circuits, standard cells, and Verilog-A models from measurement data.

You will design memory macros, evaluate device–circuit co-design, explore monolithic 3D integration, coordinate tape-outs with process partners, publish results, and mentor graduate