NAND-CMOS Device Engineer III - AI-Enabled Innovation

Micron Technology, Inc; Singapore; On-site; SGD 90,000 - 150,000; Full time

Job summary

Micron Technology, Inc in Singapore is seeking a Semiconductor Process Engineer 3 to drive the NAND-CMOS roadmap, align with product roadmaps and lead silicon experiments.

You will interface with Design Engineers to define transistor targets, deliver transistor models, and optimize layout‑constrained design rules, while collaborating with TCAD to develop strategies that meet targets and ensure reliability in final silicon.

Responsibilities

• Craft and implement the NAND‑CMOS roadmap, aligning it with product roadmaps.
• Provide direction on improving the device portfolio in terms of performance and cost effectiveness.
• Define, execute, and analyze silicon experiments for future device generations.
• Interface with Design Engineers to define transistor targets, deliver transistor models, and optimize critical layout‑constrained design rules.
• Collaborate with the TCAD simulation group to develop strategies for transistor structures that meet targets.
• Ensure transistor models are correctly targeted to anticipate final silicon.
• Define electrical test structures for transistors, isolation, design rule verification, and process monitoring.
• Ensure transistors are developed to meet required reliability standards.
• Collaborate with Manufacturing to confirm transistors perform as expected and debug yield/reliability issues.
• Mentor less experienced colleagues, fostering a collaborative work style and team spirit.
• Leverage AI tools and enable Agent‑AI solutions to automate day‑day workflow.

Job description

Micron Technology, Inc in Singapore is seeking a Semiconductor Process Engineer 3 to drive the NAND-CMOS roadmap, align with product roadmaps and lead silicon experiments.

You will interface with Design Engineers to define transistor targets, deliver transistor models, and optimize layout‑constrained design rules, while collaborating with TCAD to develop strategies that meet targets and ensure reliability in final silicon.