PD Engineer – High-Performance, Low-Power SoC Design

QRINNO PTE. LTD.; Singapore; On-site; SGD 100,000 - 145,000; Full time

Job summary

QRINNO PTE. LTD. is seeking a seasoned IC design professional to drive block-level PnR efforts, floorplanning, power integrity and timing closure for advanced nodes up to 3nm.

The role emphasizes hierarchical partitioning, CLKS tree constraints, ECO cycles, and TCL scripting to optimize tool usage and tapeouts, with experience on 7/10/14/28nm nodes valued. Experience with scan chain repartitioning, CTS, IR drop analysis, and cross-talk mitigation will be essential, along with hands-on use of

Qualifications

• Experience in netlist to GDSII flow at block, subsystem, and full chip levels.
• Hierarchical partitioning and budgeting of block-level subsystems.
• Block-level floor planning, power planning, and IR drop analysis.
• Timing signoff in loop through STA and ECO cycles at block/interface.
• CTS expertise and clock tree constraints creation to meet specs.

Skills

Netlist to GDSII

Hierarchical partitioning

Block-level floor planning

Power planning

IR drop analysis

Timing signoff

Scan chain repartitioning

CTS expertise

Clock tree constraints

TCL scripting

3nm/7nm/10nm/14nm/28nm nodes

Tools

Synopsys ICC/ICC2

Cadence Innovus

Job description

QRINNO PTE. LTD. is seeking a seasoned IC design professional to drive block-level PnR efforts, floorplanning, power integrity and timing closure for advanced nodes up to 3nm.

The role emphasizes hierarchical partitioning, CLKS tree constraints, ECO cycles, and TCL scripting to optimize tool usage and tapeouts, with experience on 7/10/14/28nm nodes valued. Experience with scan chain repartitioning, CTS, IR drop analysis, and cross-talk mitigation will be essential, along with hands-on use of