NAND Design Rule Manager

1100 Micron SemiAsiaOP Pte Ltd; Singapore; On-site; SGD 100,000 - 150,000; Full time

Job summary

1100 Micron SemiAsiaOP Pte Ltd in Singapore is seeking a Manager for NAND Design Rule/Process Integration to lead a talented team in the development and production of advanced 3D NAND technologies. This pivotal role will involve releasing design rules, managing PDK deliverables, and ensuring high-quality documentation across R&D and production efforts.

The ideal candidate will hold a PhD and have over 5 years of relevant experience in the semiconductor industry, with direct experience in PDK and design rules. Strong skills in CAD software and an understanding of semiconductor physics are essential.

Qualifications

• 5+ years of relevant experience in the semiconductor industry.
• Direct experience working with PDK and design rules.
• Skilled in CAD software and understanding of semiconductor physics.

Responsibilities

• Lead the release of design rules and PDK deliverables.
• Collaborate with various teams for new 3D NAND generations.
• Drive continuous improvement in design-rule path-finding.

Skills

CAD software (Cadence Virtuoso, K2View, Mentor Graphics DRC/RVE)

Semiconductor device physics

VLSI silicon processing

Process Integration

Yield Improvement

Education

PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science

Master’s degree with 8+ years experience

Bachelor’s degree with 13+ years experience

Job description

As the Manager for NAND Design Rule/Process Integration, you will lead a talented team to support both development and large‑scale production of advanced 3D NAND technologies. This position is essential for producing accurate design‑rule and PDK results, ensuring high quality, and maintaining strict documentation across R&D and production efforts.

Responsibilities

Lead the release of design rules and PDK deliverables; coordinate DRC waivers, mask definitions, and mask reviews for both R&D and production developments. Own program execution and achievements from kickoff through end‑of‑life. Partner with collaborators across Array & CMOS Process Integration, Devices, Layout & Build, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations. Ensure high quality and documentation for Build Rule Checks (DRCs) and drive timely disposition of deviations and exceptions. Collaborate with Yield Improvement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout‑ or database‑related process issues and prioritize corrective actions. Build and evaluate test structures to generate data for next‑generation devices and to assess process margin on current technologies. Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels. Define and track sub‑milestones within PDK/DBR/TO schedules; ensure targets are met through cross‑team coordination. Maintain strong, proactive communication with key collaborators and bring up issues early with data‑driven options. Drive continuous improvement in design‑rule path‑finding and document takeaways that improve production parts still under development.

Qualifications

PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience; or Master’s degree with 8+ years; or bachelor’s degree with 13+ years in the semiconductor industry (Process Integration, Yield Improvement, Product Engineering, Test Structure Development, or Unit Process Development). Direct experience working with PDK, design rules, and layout, including small layout assignments, is necessary. Must be skilled in CAD software such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE or their equivalents. A solid understanding of semiconductor device physics and VLSI silicon processing and integration flow is essential. Demonstrated ability to resolve complex issues and communicate clearly under pressure. Understanding of 3D NAND process flow and major NAND components (e.g., bit‑line sensing, word‑line driver, data path, and analog circuits). Familiarity with CAD group interactions, data post‑processing, and data transfer from built databases to reticles. Preferred: prior leadership experience in R&D for NAND or other memory technologies.

Equal Employment Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.