E5_MTS_SMTS NAND Design Rule Engineer in Process Integration

1100 Micron SemiAsiaOP Pte Ltd; Singapore; On-site; SGD 90,000 - 130,000; Full time

Job summary

1100 Micron SemiAsiaOP Pte Ltd in Singapore is seeking an experienced NAND Design Rule / Process Integration engineer. In this role, you will lead the release of design rules, manage PDK deliverables, and ensure high-quality documentation across R&D and production.

The ideal candidate will have a PhD in relevant fields with substantial experience in semiconductor processes and must be proficient with CAD tools. You will work closely with diverse teams to drive the development of advanced 3D NAND technologies.

Qualifications

• 5+ years relevant experience in the semiconductor industry.
• Must have proficiency with design rules and layout.
• Ability to communicate complex issues clearly.

Responsibilities

• Lead the release of design rules and PDK deliverables.
• Ensure high quality and documentation for DRCs.
• Collaborate with stakeholders to guide new 3D NAND generations.

Skills

Hands-on exposure to PDK

Strong semiconductor device physics

CAD tools proficiency

Complex issue resolution

Understanding of 3D NAND process flow

Education

PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science

Master’s degree with 8+ years experience

Bachelor’s degree with 13+ years experience

Tools

Cadence Virtuoso

K2View

Mentor Graphics DRC/RVE

Job description

Job Overview

As a E5/MTS/SMTS NAND Design Rule / Process Integration engineer, your role is to support the development and high-volume manufacturing of advanced 3D NAND technologies. This role drives design-rule and PDK deliverables, partners closely across process integration and design organizations, and ensures quality, documentation, and timely execution across R&D and production programs.

Responsibilities

• Lead the release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for both R&D and production designs.


• Own program execution and milestones from kickoff through end-of-life.


• Partner with stakeholders across Array & CMOS Process Integration, Devices, Layout & Design, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.


• Ensure high quality and documentation for Design Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.


• Collaborate with Yield Enhancement, Product Engineering, Defect Analysis, and Quality Assurance to identify layout- or database-related process issues and prioritize corrective actions.


• Design and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.


• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels.


• Define and track sub‑milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination.


• Maintain strong, proactive communication with key stakeholders and escape issues early with data-driven options.


• Drive continuous improvement in design-rule pathfinding and document learnings that improve production parts still in design.

Qualifications

• Education/experience: PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience; Master’s degree with 8+ years; or bachelor’s degree with 13+ years in the semiconductor industry (Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development).


• Hands‑on exposure to PDK, design rule, and layout (including minor layout work); proficiency with CAD tools such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE (or equivalent) is a MUST.


• Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge is a MUST.


• Demonstrated ability to resolve complex issues and communicate clearly under pressure.


• Understanding of 3D NAND process flow and major NAND components (e.g., bit‑line sensing, word‑line driver, data path, and analog circuits).


• Familiarity with CAD group interactions, data post-processing, and data transfer from design databases to reticles.


• Preferred: prior experience in R&D for NAND or other memory technologies.

About Micron Technology, Inc.

Micron Technology, Inc. is an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.