E5_MTS_SMTS NAND Design Rule Engineer in Process Integration

Micron Technology, Inc; Singapore; On-site; SGD 80,000 - 100,000; Full time

Job summary

Micron Technology, Inc. is looking for a NAND Design Rule Engineer to support the development and manufacturing of advanced 3D NAND technologies. The role involves leading design rule releases, managing milestones, and ensuring quality across R&D and production.

The ideal candidate should hold a relevant PhD or equivalent experience in the semiconductor industry, with hands-on CAD tool proficiency and strong knowledge of semiconductor device physics.

Qualifications

• 5+ years of relevant experience in the semiconductor industry.
• Demonstrated hands-on exposure to PDK and design rules.
• Understanding of 3D NAND process flow and components.

Responsibilities

• Lead the release of design rules and PDK deliverables.
• Own program execution and milestones.
• Collaborate with teams for quality documentation.

Skills

Proficiency with CAD tools (Cadence Virtuoso, K2View, Mentor Graphics DRC/RVE)

Strong semiconductor device physics knowledge

Complex issue resolution and communication under pressure

Education

PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science

Master’s degree with 8+ years of experience

Bachelor’s degree with 13+ years of experience

Tools

CAD tools

Job description

JR103598 E5_MTS_SMTS NAND Design Rule Engineer in Process Integration

As a E5/MTS/SMTS NAND Design Rule / Process Integration engineer, your role is to support the development and high-volume manufacturing of advanced 3D NAND technologies. This role drives design-rule and PDK deliverables, partners closely across process integration and design organizations, and ensures quality, documentation, and timely execution across R&D and production programs.

Responsibilities

• Lead the release of design rules and PDK deliverables; manage DRC waivers, mask definitions, and mask reviews for both R&D and production designs.
• Own program execution and milestones from kickoff through end-of-life.
• Partner with stakeholders across Array & CMOS Process Integration, Devices, Layout & Design, Modeling, Scribe & Frame, unit process areas (e.g., PHOTO/OPC/CMP), and Quality & Reliability to guide new 3D NAND generations.
• Ensure high quality and documentation for Design Rule Checks (DRCs) and drive timely disposition of deviations and exceptions.
• Collaborate with Yield Enhancement, Product Engineering, Defect Analysis, and QA to identify layout- or database-related process issues and prioritize corrective actions.
• Design and evaluate test structures to generate data for next-generation devices and to assess process margin on current technologies.
• Synthesize complex technical problems and communicate status, risks, and resolutions clearly across functions and management levels.
• Define and track sub-milestones within PDK/DBR/TO schedules; ensure targets are met through cross-team coordination.
• Maintain strong, proactive communication with key stakeholders and escape issues early with data-driven options.
• Drive continuous improvement in design-rule pathfinding and document learnings that improve production parts still in design.

Requirements

• Education/experience: PhD in Electrical Engineering, Microelectronics, Physics, or Semiconductor Materials Science with 5+ years of relevant experience; or Master’s degree with 8+ years; or bachelor’s degree with 13+ years in the semiconductor industry (Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development).
• Hands‑on exposure to PDK, design rule, and layout (including minor layout work); proficiency with CAD tools such as Cadence Virtuoso, K2View, and Mentor Graphics DRC/RVE (or equivalent) is a MUST.
• Strong semiconductor device physics and VLSI silicon processing and integration flow knowledge is a MUST.
• Demonstrated ability to resolve complex issues and communicate clearly under pressure.
• Understanding of 3D NAND process flow and major NAND components (e.g., bit‑line sensing, word‑line driver, data path, and analog circuits).
• Familiarity with CAD group interactions, data post‑processing, and data transfer from design databases to reticles.
• Preferred: prior experience in R&D for NAND or other memory technologies.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.